Table 2-9. Im Register; Table 2-10. Im Fields; Interrupt Mask Register (Im) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

2.2.2.4 Interrupt Mask Register (IM)

IM is the Interrupt Mask /Enable register. The active bits used in this register are Read/
Write and enable the interrupts. Software can read the status of the interrupt bits through
the IS Register, even if corresponding mask bits are set in this register. The Brown Out
enable is unique in that the Brown Out Interrupt can be programmed to be either an FIQ
or an IRQ. That programming is done in this register. The Interrupt Status (IS) and Masked
Interrupt Status (MIS) registers show only the status of the interrupt, not how it is config-
ured. Current configuration can be read from this register. Writing a 0 to an IM bit does not
clear the latched interrupt status in the IS register. The IS register is logically ANDed with
the IE register to create the contents of the Masked Interrupt Status (MIS) register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:7
6
5
4
3
2 EOSMSK
1 FWMSK
0 FOMSK
31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0
RO RO RO RO RO
NAME
/// Reserved Reading returns 0. Write the reset value.
Interrupt Enable
INTEN
1 = Global IRQ interrupts enabled
0 = Global IRQ interrupts masked
/// Reserved Reading returns 0. Write the reset value.
Brown Out IRQ Enable Enabling this bit allows the brownout detector to generate an
interrupt request as part of the combined TSCINTR input of the VIC.
BOIRQ
1 = Enable Brown Out IRQ to VIC
0 = Disable Brown Out IRQ to VIC
Pen IRQ Interrupt Enable
PMSK
1 = Pen IRQ enabled
0 = Pen IRQ masked
End-of-Sequence Interrupt Enable
1 = EOS IRQ enabled
0 = EOS IRQ masked
FIFO Watermark Interrupt Enable
1 = FIFO Watermark IRQ enabled
0 = FIFO Watermark IRQ masked
FIFO Overrun Interrupt Enable
1 = FIFO Overrun IRQ enabled
0 = FIFO Overrun IRQ masked
Analog-to-Digital Converter/Brownout Detector

Table 2-9. IM Register

26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFC3000 + 0x0C

Table 2-10. IM Fields

DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
///
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
0 0
RW RW
2-15