Table 15-34. Status2 Register; Table 15-35. Status2 Register Definitions; Timer 2 Status Register (Status2) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

15.2.2.16 Timer 2 Status Register (STATUS2)

The Status Register bits contain the raw interrupt status of the various interrupt generators.
Raw interrupts reflect the state of the interrupt, whether or not it is enabled. To clear a
status bit, write a 1 to that bit. This action also clears the corresponding interrupt, with the
following exception: if the timer is stopped and the Timer 2 Compare Register (T2CMP0 or
T2CMP1) value matches the Timer 2 Counter Register (CNT2), the corresponding status
bit cannot be cleared until either the Timer 2 Compare Register or the Timer 2 Counter
Register value is changed.
Writing a 0 to any of the status bits has no effect. Similarly, writing a 1 to a bit that currently
reads as 0 (no interrupt assertion) does not affect the Status Register or interrupt.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:5
4
3
2
1
0

Table 15-34. STATUS2 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 15-35. STATUS2 Register Definitions

NAME
/// Reserved Reading this field returns 0. Write the reset value.
Timer 2 Capture B Status
CAPB_ST
1 = Read: Interrupt asserted; Write: Clear interrupt
0 = Read: No interrupt asserted; Write: No effect
Timer 2 Capture A Status
CAPA_ST
1 = Read: Interrupt asserted; Write: Clear interrupt
0 = Read: No interrupt asserted; Write: No effect
Timer 2 Compare 1 Status
CMP1_ST
1 = Read: Interrupt asserted; Write: Clear interrupt
0 = Read: No interrupt asserted; Write: No effect
Timer 2 Compare 0 Status
CMP0_ST
1 = Read: Interrupt asserted; Write: Clear interrupt
0 = Read: No interrupt asserted; Write: No effect
Timer 2 Overflow Status
OVF_ST
1 = Read: Interrupt asserted; Write: Clear interrupt
0 = Read: No interrupt asserted; Write: No effect
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFC4000 + 0x58
DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RW RW RW
Timers
17 16
0 0
RO RO
1 0
0 0
RW RW
15-25