LH79524/LH79525 User's Guide
6.3.3.8 Deferred Transmission Frames (DEFTXFRM)
This is a 16-bit register containing the number of frames experiencing deferral due to
carrier sense being active on their first attempt at transmission. Frames involved in any col-
lision are not counted nor are frames that experienced a transmit underrun.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:16
15:0
6.3.3.9 Late Collisions (LATECOL)
This is an 8-bit register containing the number of frames that experience a collision after
the slot time (512 bit times) has expired. A late collision is counted twice (both as a collision
and a late collision)
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:8
7:0
Table 6-48. DEFTXFRM Register
31
30
29
28
27
0
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
11
0
0
0
0
0
RW
RW
RW
RW
RW
Table 6-49. DEFTXFRM Fields
NAME
///
Reserved Reading returns 0. Write the reset value.
DEFTXFRM Deferred Transmission Frames Deferred transmission frames count.
.
Table 6-50. LATECOL Register
31
30
29
28
27
0
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
11
///
0
0
0
0
0
RO
RO
RO
RO
RO
Table 6-51. LATECOL Fields
NAME
///
Reserved Reading returns 0. Write the reset value.
LATECOL
Late Collisions Number of late collisions.
26
25
24
23
///
0
0
0
0
RO
RO
RO
RO
10
9
8
7
DEFTXFRM
0
0
0
0
RW
RW
RW
RW
0xFFFC7000 + 0x58
FUNCTION
26
25
24
23
///
0
0
0
0
RO
RO
RO
RO
10
9
8
7
0
0
0
0
RO
RO
RO
RW
0xFFFC7000 + 0x5C
FUNCTION
Version 1.0
Ethernet MAC Controller
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
0
0
0
0
0
RW
RW
RW
RW
RW
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
LATECOL
0
0
0
0
0
RW
RW
RW
RW
RW
17
16
0
0
RO
RO
1
0
0
0
RW
RW
17
16
0
0
RO
RO
1
0
0
0
RW
RW
6-41