Table 11-2. Muxctl1 Register; Table 11-3. Muxctl1 Fields; Register Definitions - Sharp LH79524 User Manual

I/O Configuration

11.2.2 Register Definitions

11.2.2.1 Multiplexing Control 1 Register (MUXCTL1)
This Register allows software to configure pins
marked 'LH79524 Only' read as 0 with all writes 'reserved' on the LH79525.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
11-4

Table 11-2. MUXCTL1 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO

Table 11-3. MUXCTL1 Fields

BIT NAME
31:10 /// Reserved Reading returns 0. Write the reset value.
PI2/ETHERCOL Assignment
00 = PI2
9:8 PI2
01 = ETHERCOL
10 = Reserved
11 = Reserved
PI1/ETHERMDIO Assignment
00 = PI1
7:6 PI1
01 = ETHERMDIO
10 = Reserved
11 = Reserved
PI0/ETHERMDC Assignment
00 = PI0
5:4 PI0
01 = ETHERMDC
10 = Reserved
11 = Reserved
PL1/LCDVD15 Assignment (LH79524 Only)
00 = PL1
3:2 PL1
01 = LCDVD15
10 = Reserved
11 = Reserved
PL0/LCDVD14 Assignment (LH79524 Only)
00 = PL0
1:0 PL0
01 = LCDVD14
10 = Reserved
11 = Reserved
PI2/ETHERCOL through PL0/LCDVD14
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
PI2 PI1
0 0 0 0
RO RW RW RW
0xFFFE5000 + 0x00
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
PI0 PL1
0 0 0 0 0
RW RW RW RW RW
. Bits
17 16
0 0
RO RO
1 0
PL0
0 0
RW RW