Timers
15.2.2.15 Timer 2 Interrupt Control Register (INTEN2)
This register allows software to enable and disable individual interrupts as needed.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:5
4
3
2
1
0
15-24
Table 15-32. INTEN2 Register
31
30
29
28
27
0
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
11
0
0
0
0
0
RO
RO
RO
RO
RO
Table 15-33. INTEN2 Register Definitions
NAME
///
Reserved Reading this field returns 0. Write the reset value.
Timer 2 Interrupt Enable During Capture B Operation
CAPB_EN
1 = Interrupt enabled for capture B
0 = Interrupt disabled for capture B
Timer 2 Interrupt Enable During Capture A Operation
CAPA_EN
1 = Interrupt enabled for capture A
0 = Interrupt disabled for capture A
Timer 2 Interrupt Enable Upon Compare 1
CMP1_EN
1 = Interrupt enabled for compare 1
0 = Interrupt disabled for compare 1
Timer 2 Interrupt Enable Upon Compare
CMP0_EN
1 = Interrupt enabled for compare 0
0 = Interrupt disabled for compare 0
Timer 2 Interrupt Overflow Enable
OVF_EN
1 = Interrupt enabled for counter overflows
0 = Interrupt disabled for counter overflows
26
25
24
23
///
0
0
0
0
RO
RO
RO
RO
10
9
8
7
///
0
0
0
0
RO
RO
RO
RO
0xFFFC4000 + 0x54
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
0
0
0
0
0
RO
RO
RW
RW
RW
17
16
0
0
RO
RO
1
0
0
0
RW
RW