Table 10-11. Mis Register; Table 10-12. Mis Register Definitions; Masked Interrupt Status Register (Mis) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

10.2.2.5 Masked Interrupt Status Register (MIS)

This register provides the current masked status value of the corresponding interrupt.
Writing has no effect; all bits are read only. For each bit, 1 = TRUE and 0 = FALSE.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:7
6
5
4
3
2
1
0
31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0
RO RO RO RO RO

Table 10-12. MIS Register Definitions

NAME
/// Reserved Reading returns 0. Write the reset value.
SSP Protocol Error masked interrupt status Gives the Master Mode
SSPPEMIS
Protocol Error masked interrupt state.
External Codec Protocol Error masked interrupt status Gives the
ECPEMIS
Slave Mode Protocol Error masked interrupt state
Transmit Underrun Error masked interrupt status Gives the Transmit
TXUEMIS
Underrun Error masked interrupt state.
Transmit FIFO masked interrupt status (from SSP MIS:TXMIS bit) Gives
TXMIS
the Transmit FIFO masked interrupt state.
Receive FIFO masked interrupt status (from SSP MIS:RXMIS bit) Gives
RXMIS
the Receive FIFO masked interrupt state.
Receive timeout masked interrupt status (from SSP MIS:RTMIS bit)
RTMIS
Gives the Receive Timeout masked interrupt state.
Receive overrun masked interrupt status (from SSP MIS:RORMIS bit)
RORMIS
Gives the Receive Overrun masked interrupt state.

Table 10-11. MIS Register

26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFC8000 + 0x010
DESCRIPTION
Version 1.0
2
I S Converter
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 0
RO RO
10-19