Table 6-18. Rxstatus Register; Table 6-19. Rxstatus Fields; Receive Status Register (Rxstatus) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

6.3.2.7 Receive Status Register (RXSTATUS)

Read this register to obtain details of the status of a receive. Once read, individual bits may
be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:3
2 RXCOVERRUN
1
0 BUFNOTAVAIL

Table 6-18. RXSTATUS Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 6-19. RXSTATUS Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Receive Overrun The DMA Block was unable to store the receive frame to
memory. Either because the AHB bus was not granted in time or because a 'Not
OK' response was returned. The buffer will be recovered if this happens.
Read:
1 = DMA unable to store receive frame
0 = Normal operation
Write:
1 = Reset bit to 0
0 = No effect
Frame Received Indicates that one or more frames have been received and
placed in memory.
Read:
1 = One or more frames have been received and placed in memory
FRMREC
0 = No received frames
Write:
1 = Reset bit to 0
0 = No effect
Buffer Not Available An attempt was made to get a new buffer and the pointer
indicated that it was owned by the processor. The DMA will reread the pointer each
time a new frame starts until a valid pointer is found. This bit will be 1 at each attempt
that fails even if it has not had a successful pointer read since it has been cleared.
Read:
1 = Buffer not available
0 = Buffer available
Write:
1 = Reset bit to 0
0 = No effect
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFC7000 + 0x20
FUNCTION
Version 1.0
Ethernet MAC Controller
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RW
.
17 16
0 0
RO RO
1 0
0 0
RW RW
6-29