Vectored Interrupts - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

18.1.2 Vectored Interrupts

Each interrupt source line must be identified as either an IRQ type or an FIQ type using
the Interrupt Select Register (INTSELECT). FIQ interrupts are non-vectored. Once the VIC
causes the FIQ interrupt to be asserted to the core, the FIQ interrupt handler is entered
directly by loading the instruction at 0x1C independently of the VIC.
For default-vectored interrupts, set the Default Vector Address Register (DEFVECTADDR)
to the entry address of the ISR which is to handle all default-vectored interrupts.
Vectored interrupts are set up by:
• Program the Vector Address Register (VECTADDRx where 'x' is 0-15) with the entry
address of the ISR which is to handle each vectored interrupt. The easiest scheme is to
program VECTADDRx vectors 0-15 in increasing address order.
• Program the VECTCTRLx:INTSOURCE field to the interrupt source for that specific vec-
tor. Then, enable that interrupt source as a vectored interrupt using the VECTCTRLx:E
field in that register.
For example, to assign the Real Time Clock Alarm interrupt (interrupt 15) to address
0x12345678 using vector 10, program the VECTADDR10 register to address 0x12345678
(the location of the ISR for the RTC Alarm), then program VECTCTRL10 to 0x0000000F
(RTC Alarm = interrupt number 15). Then, program the VECTCTRL10:E bit to 1 to enable
the vector.
After all interrupt vector addresses and associations have been programmed, enable the
interrupts to be active, whether vectored or default-vectored, using the Interrupt Enable
Register (INTENABLE).
18.1.3 External Interrupts
All external interrupts are conditioned by the RCPC module before being presented to the
VIC. External interrupt conditioning can be configured to one of four triggers using the
RCPC Interrupt Configuration Register (see the RCPC Chapter):
• LOW-level trigger
• HIGH-level trigger
• Falling-edge trigger
• Rising-edge trigger.
On reset, all external interrupt triggers are LOW-level triggers. Therefore, make sure that
all external interrupt input signals are HIGH at reset. External edge-triggered interrupts
must be cleared using the RCPC Interrupt Clear Register. If the external interrupt is con-
figured as a level-trigger interrupt, the external interrupt must be cleared, reset, or disabled
at its source (external to the SoC).
Version 1.0
Vectored Interrupt Controller
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