Use For Ssp And Uart - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
The DMA process comprises:
1. The external request signal (DREQ) starts a peripheral DMA transfer.
2. The DMA Controller requests use of the AHB.
3. When the AHB arbiter grants the AHB to the DMA Controller, the DMA Controller fills
its FIFO with the number of data units specified by the burst length (1, 4, 8, or 16).
4. The DMA Controller continues to request the AHB following the completion of the
burst transfer. However, it may lose ownership of the AHB if a higher priority bus
master is also requesting the AHB.
5. When the AHB arbiter re-grants the AHB to the DMA Controller, the FIFO empties
(writes) its contents to the destination. The destination data width sets the width of
this data to a byte, half-word or word. The filling and emptying of the FIFO for a burst
transfer is always completed for the current stream being serviced before another
stream DMA request is serviced.
6. As DMA requests are received, the DMA Controller arbitrates between them, assign-
ing a requesting source to be serviced based on the priority indicated in Table 5-1. A
data packet transfers from the source to the DMA FIFO, then transfers from the FIFO
to the destination.
Exceptions to the DMA process are:
• When the DMA is configured to perform a memory-to-memory transfer followed by a
peripheral-to-memory transfer, the transfer starts immediately, without the DMA waiting
for the external request signal in step 1. The software workaround to this is:
– Set up a memory-to-memory access.
– Let the memory-to-memory access complete.
– Execute up the peripheral-to-memory write, but without the enable bit set.
– Perform a second write operation, with the enable bit set.
• When Stream 3 is used for memory-to-memory transfers, the transfer starts when software
sets an enable bit in the Control Register for that stream. The transfer is conducted in
bursts, with the bursts executing back-to-back until the required number of data units are
transferred. The DMA Controller retains ownership of the AHB between successive bursts,
unless the AHB Arbiter de-grants the DMA Controller for a higher priority bus master.

5.1.1 Use for SSP and UART

The SSP:DCR:RXDMAE bit, SSP:DCR:TXDMAE, UART:DMACTRL:RXDMAEN, and
UART:DMACTRL:TXDMAEN bits are not automatically cleared for standard Stream 0
through 3 DMA operations, respectively. These bits should be explicitly cleared by soft-
ware as soon as possible following DMA completion.
On initiating a DMA operation the DMAC:CTRL:ENABLE bit should be set before any of
the above mentioned bits are set.
5.1.2 Changing Mode from Memory to Peripheral
When changing from a Memory-to-Memory (MTM) transfers to a Peripheral-to-Memory (either
MTP or PTM transfers), the DMA Controller must be disabled before setting up the Peripheral
transfer. Otherwise, the PTM or MTP transfer will start immediately, without a trigger.
For example, allow the MTM transfer to complete, then disable the DMA, configure the
PTM transfer with the DMA disabled, then enable the transfer.
Version 1.0
Direct Memory Access Controller
5-3