Table 7-17. Dynmctrl Register; Table 7-18. Dynmctrl Fields; Dynamic Memory Control Register (Dynmctrl) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

7.5.2.4 Dynamic Memory Control Register (DYNMCTRL)

The Dynamic Memory Control Register is used to control dynamic memory operation. The
control bits can be altered during normal operation.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:14
13
12:9
8:7
6
5 MEMCC
4:3
2
1
0

Table 7-17. DYNMCTRL Register

31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
/// DP
0 0 0 0
RW RW RW RW RW

Table 7-18. DYNMCTRL Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Low-Power SDRAM Deep-Sleep Mode
DP
1 = Enter deep power down mode
0 = Normal operation
/// Reserved Reading returns 0. Write the reset value.
SDRAM Initialization
00 = issue SDRAM NORMAL operation command
INIT
01 = issue SDRAM MODE command
10 = issue SDRAM PALL (precharge all) command
11 = issue SDRAM NOP (no operation) command
/// Reserved Reading returns 0. Write the reset value.
Memory Clock Control Disabling SDCLK can be performed if there are no SDRAM
memory transactions. When enabled, this field can be used in conjunction with the dynamic
memory clock control (CS) field.
1 = SDCLK disabled
0 = SDCLK enabled
/// Reserved Reading returns 0. Write the reset value.
Self-Refresh Request Software can command the EMC into self-refresh by writing
a 1 to this bit. Writing 0 to this bit returns the memory controller to normal mode. The Self-
refresh Acknowledge bit (SA) in the Status register must be polled to determine the current
operating mode of the memory controller. Note that static memory may be accessed nor-
SR
mally while dynamic memory is in self-refresh mode.
1 = Enter Self-Refresh Mode
0 = Normal Mode
Dynamic Memory Clock Select When clock control is 0 the output clock SDCLK is
stopped when there are no SDRAM transactions. The clock is also stopped during self-
refresh mode.
CS
1 = SDCLK runs continuously
0 = SDCLK stops when all SDRAMs are idle and during self-refresh mode.
Dynamic Memory Clock Enable Clock enable must be HIGH during SDRAM initialization
CE
1 = All clock enables are driven HIGH continuously
0 = Clock enable signal of idle devices are deasserted to save power
26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
/// INIT
0 0 0 0 0
RW RW RW RW
0xFFFF1000 + 0x020
FUNCTION
Version 1.0
External Memory Controller
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
/// /// SR
0 0 0 0 1
RW RW RW RW RW
17 16
0 0
RO RO
1 0
CS CE
1 0
RW RW
7-33