Sharp LH79524 User Manual page 268

LH79524/LH79525 User's Guide
BITS NAME
8
7
6
5:4
3
2
1:0
Table 7-53. SCONFIGx Fields (Cont'd)
Extended Wait Extended wait uses the WAIT register to time both the read and
write transfers rather than the SWAITRD and SWAITWR registers. This enables
much longer transactions.
EW
1 = Extended wait enabled
0 = Extended wait disabled
Byte Lane State This bit allows connection of different storage widths. For byte-
wide static memories, the nBLE[3:0] signal is usually connected to nWE. In this
case for reads all the nBLE[3:0] bits must be HIGH. This means that the BLS bit
must be 0. 16-bit wide static memory devices usually have the nBLE[3:0] signals
connected to the nUB and nLB (upper byte and lower byte) signals in the static
memory. In this case a write to a particular byte must assert LOW the appropriate
nUB or nLB signal. For reads, all the nUB and nLB signals must be asserted LOW
so that the bus is driven. In this case the BLS bit must be HIGH.
BLS
IMPORTANT: When accessing NAND Flash, this bit must be programmed to 1
by the Boot ROM code for proper operation.
Writes
1 = The active bits in nBLE[3:0] are LOW
0 = The active bits in nBLE[3:0] are HIGH
Reads
1 = The active bits in nBLE[3:0] are LOW
0 = All the bits in nBLE[3:0] are HIGH
Chip Select Polarity
PC
1 = active HIGH Chip Select
0 = active LOW Chip Select
/// Reserved Read undefined, must write as zeros.
Page Mode In page mode the memory controller can burst up to four external
accesses. Therefore devices with asynchronous page mode burst of four or
higher are supported. Asynchronous page mode burst two devices are not
PM
supported and must be accessed normally.
1 = asynchronous page mode enabled
0 = disabled
/// Reserved Read undefined, must write as zeros.
Memory Width Set this to the memory width of the bank, not the devices. For
example, if two 8-bit devices are configured as a 16-bit memory bank, choose 01.
00 = 8-bit
MW
01 = 16-bit
10 = 32-bit
11 = reserved
FUNCTION
Version 1.0
External Memory Controller
7-53