Table 13-28. Pclksel0 Register; Table 13-29. Pclksel0 Fields; Peripheral Clock Select Register 0 (Pclksel0) - Sharp LH79524 User Manual

Reset, Clock, and Power Controller

13.2.2.12 Peripheral Clock Select Register 0 (PCLKSEL0)

This register allows selection of the clock source for the UARTs.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
13-22

Table 13-28. PCLKSEL0 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 13-29. PCLKSEL0 Fields

BITS NAME
31:3 /// Reserved Reading returns 0. Write the reset value.
UART2 Clock Source
2 UART2
1 = System Clock (HCLK)
0 = Crystal oscillator output
UART1 Clock Source
1 UART1
1 = System Clock (HCLK)
0 = Crystal oscillator output
UART0 Clock Source
0 UART0
1 = System Clock (HCLK)
0 = Crystal oscillator output
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFE2000 + 0x30
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RW
17 16
0 0
RO RO
1 0
0 0
RW RW