Table 13-19. Cpuclkpre Register; Table 13-20. Cpuclkpre Fields; Table 13-21. Cpuclkpre Register Values; Cpu Clock Prescaler Register (Cpuclkpre) - Sharp LH79524 User Manual

Reset, Clock, and Power Controller

13.2.2.8 CPU Clock Prescaler Register (CPUCLKPRE)

FCLK is the CPU Clock. This register allows a divisor to be programmed that is used to
divide the system PLL frequency to derive FCLK. The prescaled FCLK frequency is
defined by:
ƒ(FCLK)
Following reset, the prescaler is programmed to divide by 30. Table 13-21 shows example
values for FDIV. The CPU clock must always be greater than or equal to the system bus
clock. Thus when changing clock dividers, the CPU frequency should be increased
BEFORE, decreased AFTER, and always kept at least equal to the system bus frequency.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:4
3:0
13-18
⎛ ƒ(SystemPLL) ⎞
ƒ ------------------------------------- -
=
⎝ ⎠
×
2 FDIV

Table 13-19. CPUCLKPRE Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 13-20. CPUCLKPRE Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
FCLK Divisor Program with the divisor for the HCLK prescaler. All FDIV
FDIV
combinations are valid except 0b0000.

Table 13-21. CPUCLKPRE Register Values

FDIV
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
:
0b1111 (default)
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFE2000 + 0x1C
DESCRIPTION
DIVISOR VALUE
—
2
4
6
8
10
:
30
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 1 1
RO RO RO RW RW
ƒ(FCLK)
Invalid
ƒ(System PLL)/2
ƒ(System PLL)/4
ƒ(System PLL)/6
ƒ(System PLL)/8
ƒ(System PLL)/10
:
ƒ(System PLL)/30
17 16
0 0
RO RO
1 0
FDIV
1 1
RW RW