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Chapter 13
Reset, Clock, and Power
Controller
The Reset, Clock, and Power Controller (RCPC) manages the operating mode, generates
appropriately prescaled clocks, and correctly times reset execution. The RCPC:
• Manages five Power Modes for minimizing power consumption: Active, Standby, Sleep,
Stop1, and Stop2
• Generates the System Clock (HCLK) from either the System PLL clock or the PLL-
bypassed (System Clock Oscillator) clock, prescaled by 2, 4, 6, 8, 10, 12...30
• Generates the CPU clock (FCLK) from either the System PLL clock or the PLL-bypassed
(System Clock Oscillator) clock, prescaled by 2, 4, 6, 8, 10...30
• Generates the three UART clocks from System Clock Oscillator clock
• Generates the 1 Hz Real Time Clock (RTC)
• Generates the Liquid Crystal Display (LCDDCLK) clock from HCLK, prescaled by 1, 2,
4, 8, 16, 32, 64, 128, or 256
• Generates the Synchronous Serial Port (SSPCLK) clock from HCLK or the System
Clock Oscillator clock, prescaled by 1, 2, 4, 8, 16, 32, or 64, 128, or 256
• Select the USB clock from HCLK or the USB PLL Clock, prescaled by 1, 2, or 4
• Generates the ADC clock from HCLK or the System Clock Oscillator clock, prescaled by
1, 2, 4, 8, 16, 32, or 64, 128, or 256
• Provides a selectable external clock output (CLKOUT)
• Generates system reset based on an external reset, watchdog timer reset, or soft reset
• Configures eight HIGH/LOW-level or rising/falling edge-trigger external interrupts and
converts them to HIGH-level trigger interrupt outputs required by the Vectored Interrupt
Controller (VIC)
• Generates remap outputs used by the memory map decoder
• Contains the Chip ID register
• Supports external or Watchdog reset status.
• Configures the PLL to generate System Clock from the System Clock Oscillator
Figure 13-1 shows a block diagram of the RCPC.
Version 1.0
13-1
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