Figure 3-1. Boot Controller Block Diagram - Sharp LH79524 User Manual

Chapter 3
Boot Controller
The Boot Controller is the same for both the LH79524 and LH79525. All references in this
chapter apply to both devices.
The Boot Controller provides a glueless interface to external NAND Flash devices and
support for memory-mapped peripherals or NAND flash devices when performing AHB
burst read accesses of undetermined length.
By monitoring external boot pins at power-on reset, the Boot Controller supports:
• Booting from 8-, 16-, or 32-bit memory
• Configuration of the byte-lane boot state for nCS1
• Booting from alternate external devices (e.g., NAND Flash, UART, I
Figure 3-1 shows the Boot Controller block diagram.
ADVANCED
PERIPHERAL
BUS (APB)
AMBA
REGISTER
APB
BLOCK
INTERFACE

Figure 3-1. Boot Controller Block Diagram

Version 1.0
FROM AHB AHB
DECODER
CONTROL
EXTERNAL
PERIPHERAL
INTERFACE
PC[7:4] EXTERNAL
ADDRESS and
CONTROL
2
C).
AHB
CONTROL
CONTROL
TO nCS1
nCS1
OVERRIDE
TO BOOT ROM
BOOT BOOT
CONTROL CONTROL
NAND
NAND FLASH:
FLASH
nFRE, nFWE
CONTROL
LH79525-61
3-1