Table 16-30. Uartmis Register; Table 16-31. Uartmis Fields; Masked Interrupt Status Register (Uartmis) - Sharp LH79524 User Manual

UARTs

16.3.2.12 Masked Interrupt Status Register (UARTMIS)

UARTMIS is the Masked Interrupt Status Register. On a read, this register returns the cur-
rent masked status value of the corresponding interrupt. A write has no effect.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:11
10
9
8
7
6
5
16-24

Table 16-30. UARTMIS Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO

Table 16-31. UARTMIS Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Overrun Error Masked Interrupt Status Specifies the masked interrupt
state of the UARTOEINTR interrupt.
OEMIS
1 = Interrupt pending
0 = No interrupt, or interrupt masked
Break Error Masked Interrupt Status Specifies the masked interrupt state
of the UARTBEINTR interrupt.
BEMIS
1 = Interrupt pending
0 = No interrupt, or interrupt masked
Parity Error/Address Received Masked Interrupt Status Specifies the
masked interrupt state of the UARTPEARINTR interrupt.
PEARMIS
1 = Interrupt pending
0 = No interrupt, or interrupt masked
Framing Error Masked Interrupt Status Specifies the masked interrupt
state of the UARTFEINTR interrupt.
FEMIS
1 = Interrupt pending
0 = No interrupt, or interrupt masked
Receive Timeout Masked Interrupt Status Specifies the masked interrupt
state of the UARTRTINTR interrupt.
RTMIS
1 = Interrupt pending
0 = No interrupt, or interrupt masked
Transmit Timeout Masked Interrupt Status Specifies the masked inter-
rupt state of the UARTTXINTR interrupt.
TXMIS
1 = Interrupt pending
0 = No interrupt, or interrupt masked
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
RO RO RO RO
UART 0: 0xFFFC0000 + 0x040
UART 1: 0xFFFC1000 + 0x040
UART 2: 0xFFFC2000 + 0x040
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
///
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
///
0 0
RO RO