Table 16-34. Dmactrl Register; Table 16-35. Dmactrl Fields; Uart0 Dma Control Register (Dmactrl) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

16.3.2.14 UART0 DMA Control Register (DMACTRL)

UART0 DMACTRL is the UART0 DMA Control Register. It allows control of certain UART
DMA functions.
The RXDMAEN, and TXDMAEN bits are not automatically cleared for standard Stream 0
through 3 DMA operations, respectively. These bits should be explicitly cleared by soft-
ware as soon as possible following DMA completion.
On initiating a DMA operation the DMAC:CTRL:ENABLE bit should be set before either of
the above mentioned bits are set.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
15:3
2
1 TXDMAEN
0 RXDMAEN

Table 16-34. DMACTRL Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 16-35. DMACTRL Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
DMA on Error
1 = Disables the DMA receive request output when the UART Error Interrupt is
DMAOE
asserted
0 = Does not disables the DMA receive request output when the UART Error
Interrupt is asserted
Transmit DMA Enable
1 = Enables the DMA for the transmit FIFO
0 = Disables the DMA for the transmit FIFO
Receive DMA Enable
1 = Enables the DMA for the receive FIFO
0 = Disables the DMA for the receive FIFO
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
UART 0: 0xFFFC0000 + 0x048
DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RW
UARTs
17 16
0 0
RO RO
1 0
0 0
RW RW
16-27