Table 5-8. Destlo Register; Table 5-9. Destlo Fields; Table 5-10. Desthi Register; Table 5-11. Desthi Fields - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

5.2.2.2 Destination Base Registers (DESTLO and DESTHI)

The two 16-bit Destination Base Register contain the 32-bit destination base address for
the next DMA transfer. When the DMA Controller is enabled, the contents of the Destina-
tion Base Address Registers load into the Current Destination Address Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:0
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:0

Table 5-8. DESTLO Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW
NAME
/// Reserved Reading returns 0. Write the reset value.
Low Order Destination Address This field contains the lower 16-bits of the
DESTLO
address for the destination of data for the next DMA transfer.

Table 5-10. DESTHI Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW
NAME
/// Reserved Reading returns 0. Write the reset value.
High Order Destination Address This field contains the upper 16-bits of the
DESTHI
address for the destination of data for the next DMA transfer.
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
DESTLO
0 0 0 0
RW RW RW RW
DATASTREAM x BASE + 0x008

Table 5-9. DESTLO Fields

DESCRIPTION
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
DESTHI
0 0 0 0
RW RW RW RW
DATASTREAM x BASE + 0x00C

Table 5-11. DESTHI Fields

DESCRIPTION
Version 1.0
Direct Memory Access Controller
22 21 20 19
0 0 0 0
RO RO RO RO RO
6 5 4 3
0 0 0 0
RW RW RW RW RW
22 21 20 19
0 0 0 0
RO RO RO RO RO
6 5 4 3
0 0 0 0
RW RW RW RW RW
18 17 16
0 0 0
RO RO
2 1 0
0 0 0
RW RW
18 17 16
0 0 0
RO RO
2 1 0
0 0 0
RW RW
5-7