Phy Maintenance - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide Ethernet MAC Controller

6.2.1.5 PHY Maintenance

The PHYMAINT register enables the EMAC to communicate with a PHY using the MDIO
interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are con-
figured for the same speed and either half- or full-duplex configuration.
The PHYMAINT register is implemented as a shift register. Writing to the register starts a
shift operation that is signalled as complete when the NETSTATUS:PHYIDLE bit is set to
1 (about 2,000 HCLK cycles later, when the NETCONFIG:DIV field is set to 1). An interrupt
is generated as this bit is set.
During this time, the MSB of the PHYMAINT register is output on the ETHERMDIO pin and
the LSB updated from the ETHERMDIO with each ETHERMDC cycle. This causes the
transmission of a PHY management frame on MDIO.
Reading during the shift operation returns the current contents of the shift register. At the
end of the management operation, the bits will have shifted back to their original locations.
For a read operation, the data bits are updated with data read from the PHY.
ETHERMDC should not toggle faster than 2.5 MHz. ETHERMDC is generated by dividing
down HCLK. The NETCONFIG:DIV bits set the divisor for HCLK to produce ETHERMDC.
The default is 32, which is acceptable for HCLK running up to 80 MHz.
6.2.1.6 Interrupts
There are 14 interrupt conditions that are detected within the EMAC. These are ORed to
make a single interrupt, which is presented to the Vectored Interrupt Controller (VIC), if
interrupts are enabled. To ascertain which interrupt has been generated, read the Interrupt
Status Register (INSTATUS). Note that this register clears when read.
At reset all interrupts are disabled. To enable an interrupt, write to Interrupt Enable Regis-
ter (ENABLE) with the pertinent interrupt bit programmed to 1. To disable an interrupt, write
to Interrupt Disable Register (DISABLE) with the pertinent interrupt bit programmed to 1.
To determine whether an interrupt is enabled or disabled, read Interrupt Mask Register
(MASK): if the bit is 1, the interrupt is disabled.
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