Figure 10-5. I 2 S Master Mode Transmission Block Diagram; Figure 10-6. I 2 S Master Mode Transmission Timing Diagram; Chapter 10 - I 2 S Converter; Transmission - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

10.1.3 Transmission

10.1.3.1 Master Mode Transmission
During Master Mode transmission, the I
data (on the PB5/SSPTX/I2STXD/UARTTX0/UARTIRTX0 pin) to the external CODEC.
The Master Mode clock is the SSP master mode clock, SSPCLKOUT, inverted as indi-
cated by the CTRL:CLKINV bit.
The SSP frame output pulse is converted to a level to generate PB2/SSPFRM/I2SWS. If
WSDEL is set to 1, then PB2/SSPFRM/I2SWS is delayed by one clock so that it transitions
with the MSB of the transmitted data.
The data to be transmitted is received by the I
one clock and then transmitted on the PB5/SSPTX/I2STXD/UARTTX0/UARTIRTX0 pin.
Note that when in master mode, the I
tinuous mode. If the transmit FIFO is starved, the SSP will operate in single-word transfer
mode in which is stops generating SSPCLKOUT and SSPFSSOUT as soon as the transfer
of the last word in the FIFO has completed. The I
form its conversion.
I2SCLKOUT
SSPFSSOUT
SSPTXD
I2SFSSOUT
(WSDEL = 0)
I2SFSSOUT
(WSDEL = 1)
I2STXD
SSP
(MASTER)
SSPCLKOUT
SSPFSSOUT
SSPTXD
2
Figure 10-5. I S Master Mode Transmission Block Diagram
MSB1
MSB1
2
Figure 10-6. I S Master Mode Transmission Timing Diagram
2
S converter supplies the clock, frame output, and
2
S converter from the SSP. It is delayed by
2
S Converter requires that the SSP operate in TI con-
2
S Converter needs these signals to per-
2
I S CONVERTER
(MASTER)
I2SCLKOUT
I2SFSSOUT
I2STXD
14 13 12 2
14 13 3
Version 1.0
I
EXTERNAL CODEC
(SLAVE)
SCK
WS
SD
1 LSB1 MSB2 14 13
2 1 LSB1 MSB2 14
2
S Converter
LH79525-95
12 11
13 12
LH79525-96
10-5