Table 16-32. Uarticr Register; Table 16-33. Uarticr Fields; Interrupt Clear Register (Uarticr) - Sharp LH79524 User Manual

UARTs

16.3.2.13 Interrupt Clear Register (UARTICR)

UARTICR is the Interrupt Clear Register. The active bits used in this register are Write
Only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:15
10
9
8
7
6
5
4
3:2
1
0
16-26

Table 16-32. UARTICR Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO

Table 16-33. UARTICR Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Overrun Error Interrupt Clear
OEIC
1 = Clears the interrupt
0 = No effect
Break Error Interrupt Clear
BEIC
1 = Clears the interrupt
0 = No effect
Parity Error/Address Received Interrupt Clear
PEARIC
1 = Clears the interrupt
0 = No effect
Framing Error Interrupt Clear
FEIC
1 = Clears the interrupt
0 = No effect
Receive Timeout Interrupt Clear
RTIC
1 = Clears the interrupt
0 = No effect
Transmit Interrupt Clear
TXIC
1 = Clears the interrupt
0 = No effect
Receive Interrupt Clear
RXICR
1 = Clears the interrupt
0 = No effect
/// Reserved Reading returns 0. Write the reset value.
CTS0 Interrupt Clear (only for UART0)
CTS0IC
1 = Clears the interrupt
0 = No effect
/// Reserved Reading returns 0. Write the reset value.
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
WO WO WO WO
UART 0: 0xFFFC0000 + 0x044
UART 1: 0xFFFC1000 + 0x044
UART 2: 0xFFFC2000 + 0x044
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
///
0 0 0 0 0
WO WO WO RO RO
17 16
0 0
RO RO
1 0
///
0 0
WO RO