Sharp LH79524 User Manual page 48

LH79524/LH79525 User's Guide
NAME
CLCD Clock
Serial Interface
Clock (UART[2:0] )
Counter/Timer
Clocks
RTC Clock
Clock Output
(CLKOUT)
Table 1-2. Clock Descriptions (Cont'd)
FREQUENCY
(MAX.)
This clock controls the data rate for pixel transfers to an external LCD
panel. This clock can be separately enabled, disabled and prescaled.
50.803 MHz
Source can be divided by 2
for power savings.
These clocks control the data transfer rates over the three UART inter-
20 MHz faces. These clocks are all separate and can be separately enabled
and disabled. Clock source can be selected from HCLK or CLK OSC.
These clocks control the transition rates for the internal timers.
The source can be selected from HCLK or the External Timer input
25.415 MHz
(CTCLK). Each timer is either clocked by CTCLK or HCLK divided by
n (0 < n ≤ 8).
2
This clock controls the transition rate for the internal real-time clock.
32.768 kHz The source can be selected from the 1 Hz Clock, RTC OSC, CLK PLL,
or an External RTC Clock connected to the XTAL32IN pin.
This output clock is available on pin CLKOUT for use with external
50.803 MHz
peripherals. Input source can be FCLK, HCLK, or CLK OSC.
Version 1.0
DESCRIPTION
n (n ≤ 8). This clock can be individually halted
Overview
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