1.3.1.2 Synchronous And Asynchronous Bus Clocking Modes; 1.3.1.3 Fastbus Extension Bus Clocking Mode; Figure 1-3. Fastbus Clocking Mode - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide Overview

1.3.1.2 Synchronous and Asynchronous Bus Clocking Modes

Although the frequency of FCLK must always be greater than (or equal to) HCLK, the two
Standard modes vary the relationship between these two clock signals. In the Synchro-
nous Mode, the FCLK frequency must be programmed to be an even integer multiple of
the HCLK frequency. Bus accesses in the Synchronous Mode require a re-synchronization
delay of at least one wait state. In the Asynchronous Mode the harmonic relationship
between the clocks need not be maintained; the two clock signals may be of unrelated fre-
quency. Bus accesses in the Asynchronous Mode require a minimum re-synchronization
delay of two wait states.

1.3.1.3 Fastbus Extension Bus Clocking Mode

Designs involving frequent accesses of high-speed memory may benefit by using the
Fastbus Extension Mode. This inherently synchronous mode clocks the core, cache, and
AHB at the same frequency. Where the Standard modes utilized two different clocks, the
Fastbus mode operates the core, cache, and AHB interface with two signals derived from
the same source; essentially the same clock. Figure 1-3 shows the Fastbus Extension
Mode clocking arrangement. The Fastbus Extension Mode does not require re-synchroni-
zation delays.
The Fastbus Extension Mode is useful for applications involving frequent AHB accesses.
Although the core's frequency is limited by the AHB maximum frequency, the Fastbus
Extension Mode avoids the wait-state penalties imposed by the Standard modes.
ARM720T
CORE CACHE
HCLK_CPU
COMMON CLOCK
SOURCE
HCLK
AHB
INTERFACE
ADVANCED
HIGH-PERFORMANCE
BUS (AHB)
NOTE: This is a conceptual drawing
LH79525-50

Figure 1-3. Fastbus Clocking Mode

Version 1.0 1-7