Table 5-14. Ctrl Register; Table 5-15. Ctrl Fields; Control Register (Ctrl) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

5.2.2.4 Control Register (CTRL)

The Control Register contains the configuration of the DMA Controller. Constraints on the
field values based on the stream type are defined in Table 5-18. Where a value appears
in this table, that is the only valid value for that stream, and the field must be programmed
to this value.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:14
13
12
11
10
9
8:7
31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
/// DIR /// M2M
0 0 0 0 0
RO RO RW RO RW
NAME
/// Reserved Reading returns 0. Write the reset value.
Peripheral is Source or Destination
DIR
1 = Peripheral is the destination
0 = Peripheral is the source
/// Reserved Reading returns 0. Write the reset value.
Stream 3 Memory Transfer Selects memory-to-memory transfer for
Stream 3. Ignored for data streams[2:0].
1 = Stream 3 is configured for memory-to-memory transfer. The DMA
M2M
Controller disregards any request from UART0TX and transfers data
from source to destination as fast as possible until MaxCnt expires
0 = Stream 3 is not configured for memory-to-memory transfer
/// Reserved Reading returns 0. Write the reset value.
Current Source/Destination Loading Determines whether the Current
Source Address Register and the Current Destination Address Register load
from the Source Base Registers and the Destination Base Registers, re-
spectively, when the DMA Controller is enabled.
1 = Incremental Address Mode for source and destination. Registers are not
ADMODE
reloaded from their respective Base Address Registers when the DMA
Controller is enabled
0 = Wrapping Address Mode for source and destination. Registers load from
their respective Base Address Registers when the DMA Controller is
enabled. (default)
DMA-to-Destination Data Width Specifies the DMA-to-destination data
DESIZE
width. See Table 5-16.

Table 5-14. CTRL Register

26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
/// DESIZE
0 0 0 0
RO RW RW RW
0xFFFE1000 + 0x14

Table 5-15. CTRL Fields

DESCRIPTION
Version 1.0
Direct Memory Access Controller
22 21 20 19 18
0 0 0 0
RO RO RO RO RO
6 5 4 3
SOBURST SOSIZE
0 0 0 0
RW RW RW RW RW
17 16
0 0 0
RO RO
2 1 0
0 0 0
RW RW
5-9