Table 5-16. Dma Data Width; Table 5-17. Dma Burst Size - Sharp LH79524 User Manual

Direct Memory Access Controller
BIT
6:5
4:3
2
1
0
5-10
Table 5-15. CTRL Fields (Cont'd)
NAME
Peripheral Burst Size Defines the number of peripheral data units in the
peripheral burst. Using the peripheral as the destination, the DMA interface
SOBURST automatically reads the correct number of source words to compile a trans-
action. When stream 3 is configured as a memory-to-memory transfer,
SOBURST is the source-side burst length. Table 5-16 shows valid values.
Source-to-DMA Data Width See Table 5-16. Note that Stream 0
SOSIZE
(SSPRX) only supports half-word source data width.
Current Destination Register Increment Enables the Current
Destination Register increment after each DMA-to-destination data transfer.
DEINC
1 = Current Destination Register is incremented
0 = Current Destination Register remains unchanged
Current Source Register Increment Enables a Current Source Register
increment after each source-to-DMA data transfer.
1 = Current Source Register increments as data transfers from a source to
SOINC
the DMA. The value increments at the end of the address phase of the
AHB transfer
0 = Current Source Register remains unchanged, holding the same value
during the entire DMA transfer
DMA Controller Enable/Disable Enables or disables the DMA Controller.
The Source Base, Destination Base, and Maximum Count Registers must be
set before the DMA is enabled. The state machine clears this bit when a data
transfer finishes. If the software resets this bit during a transfer, that stream
ENABLE
interface will be reset.
1 = DMA data transfer is enabled
0 = DMA data transfer is disabled

Table 5-16. DMA Data Width

SOSIZE/DESIZE

Table 5-17. DMA Burst Size

SOBURST
DESCRIPTION
AHB DATA WIDTH
00 1 byte
01 1 half-word (2 bytes)
10 1 word (4 bytes)
11 Reserved
AHB BURST TYPE
00 Single
01
10
11
Version 1.0
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