Table 16-1. Control Bits To Enable And Disable Hardware Flow Control - Sharp LH79524 User Manual

UARTs
16.1.7 Hardware Flow Control
Hardware flow control is fully selectable, and allows control of the serial data flow by using
the nUARTRTS0 output and nUARTCTS0 input signals. Enabling flow control pins is made
in the MUXCTL6:PB1 and MUXCTL6:PB0 fields, which is described in Table 11-18.
When the RTS flow control is enabled, the nUARTRTS0 signal is asserted until the receive
FIFO is filled up to the programmed watermark level. When the CTS flow control is
enabled, the transmitter can only transmit data when the nUARTCTS signal is asserted.
The hardware control is selectable through bits 14 (RTSEN) and 15 (CTSEN) in the Con-
trol Register (UARTCR); see Section 16-22. Table 16-1 shows the bit settings to enable
RTS and CTS flow control both simultaneously, and independently.
16.1.7.1 RTS Flow Control
The RTS flow control logic is linked to the programmable receive FIFO watermark levels.
When RTS flow control is enabled, the nUARTRTS0 is asserted until the receive FIFO is
filled up to the watermark level. When the receive FIFO watermark level is reached, the
nUARTRTS0 signal is deasserted, indicating that the FIFO is full and data transmission
should cease after transmission of the current character.
The nUARTRTS0 signal is reasserted when the receive FIFO has been emptied to less
than the watermark level. If RTS flow control is disabled and the UART is still enabled, data
is received until the receive FIFO is full, or until no more data is transmitted to it.
16.1.7.2 CTS Flow Control
If CTS flow control is enabled, the transmitter checks the nUARTCTS0 signal before trans-
mitting the next byte. If the nUARTCTS0 signal is asserted, it transmits the byte; otherwise
transmission does not occur. The data continues to be transmitted while nUARTCTS0 is
asserted, and the transmit FIFO is not empty. If the transmit FIFO is empty and the
nUARTCTS0 signal is asserted, no data is transmitted.
If the nUARTCTS0 signal is deasserted and CTS flow control is enabled, the current char-
acter transmission completes before stopping. If CTS flow control is disabled and the UART
is enabled, data continues to be transmitted until the transmit FIFO is empty.
16.1.8 Programming Control Registers
A UART must be disabled before any of the Control Registers are programmed. When the
UART is disabled in the middle of transmission or reception, it completes the current char-
acter operation before stopping.
16-6

Table 16-1. Control bits to enable and disable hardware flow control

UARTCR:CTSEN UARTCR:RTSEN
1
1
0
0
1 Both RTS and CTS flow control enabled.
0 Only CTS flow control enabled.
1 Only RTS flow control enabled.
0 Both RTS and CTS flow control disabled.
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LH79524/LH79525 User's Guide
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