Table 13-12. Rststatus Register; Table 13-13. Rststatus Fields; Reset Status Register (Rststatus) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

13.2.2.5 Reset Status Register (RSTSTATUS)

This register provides the reset status of the SoC, containing both the external reset status
and the WDT timeout reset status. Following external reset, the EXT bit is 1 and the WDTO
bit is 0. At WDT timeout, only the WDTO bit is 1. The EXT and WDTO bits remain 1 until
they are cleared by writing to the Reset Status Clear register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:2
1
0

Table 13-12. RSTSTATUS Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 13-13. RSTSTATUS Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
WDT Timeout
WDTO
1 = WDT timeout has occurred
0 = No WDT timeout has occurred since the flag was last cleared
External Reset
EXT
1 = External reset has occurred
0 = No external reset has occurred since the flag was last cleared
Reset, Clock, and Power Controller
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFE2000 + 0x10
DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
EXT
0 1
RO RO
13-15