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Color Liquid Crystal Display Controller
4.3.4 Pixel Serializer
The pixel serializer reads the 32-bit-wide LCD data from the output port of the LCD DMA
FIFO and extracts 12, 8, 4, 2, or 1 bits per pixel (bpp) data, depending on the operating
mode. In Dual Panel Mode, data alternately is read from the upper and lower LCD DMA
FIFOs. Depending on the operating mode, the extracted data is either used to point to a
color/grayscale value in the palette RAM or directly applied to an LCD panel input.
4.3.5 How Pixels are Stored in Memory
Table 4-1 shows the pixel arrangement on a display, with the first 32 pixels labeled p0
through p31. Table 4-2 and Table 4-3 show the data structure in each DMA FIFO word cor-
responding to the bpp combinations. The required data for each panel display pixel must
be extracted from the data word. The first pixel value in the frame corresponds to the color
value encoded in P0 (see Table 4-3), the second corresponds to P1, the third to P2, and
so on (continuing in Table 4-2).
BPP
1
p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16
2
4
8
1
12
2
16
NOTES:
1. LH79525 with 12-Bit CLCDC
2. LH79524 with 16-Bit CLCDC
4-6
Table 4-1. Pixel Display Arrangement
Table 4-2. Frame Buffer Pixel Storage Format [31:16]
31
30
29
28
27
p15
p14
1
0
1
0
1
p7
3
2
1
0
3
p3
7
6
5
4
3
11
10
9
8
15
14
13
12
11
DMA FIFO OUTPUT BITS
26
25
24
23
p13
p12
p11
0
1
0
1
p6
2
1
0
3
2
1
0
7
p1
7
6
5
p1
10
9
8
7
Version 1.0
LH79524/LH79525 User's Guide
22
21
20
19
18
p10
p9
0
1
0
1
0
p5
2
1
0
3
2
p2
6
5
4
3
2
4
3
2
1
6
5
4
3
2
17
16
p8
1
0
p4
1
0
1
0
0
1
0
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