Interrupt Handling - Sharp LH79524 User Manual

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2
I
C Module

9.1.2 Interrupt Handling

In Slave mode, the I
ICDATA register, and generates ACK pulses at the appropriate times. In short, the inter-
face hardware handles the bit-level operation of the protocol.
Interrupts are generated on both receive and transmit data, in a way similar to typical serial
data interrupts. On transmit, when the data in ICDATA has been sent and the I
is ready to accept another byte of transmit data, a transmit interrupt is generated. On
receive, when new data is received over the interface and placed into the ICDATA register,
a receive interrupt is generated.
For the purposes of interrupt generation, no distinction is made between address bytes
and data bytes. However, in Slave mode, the I
to it. In 7-bit addressing mode, addresses that do not match that of the I
generate interrupts. Nor do any following data transactions.
In 10-bit addressing mode, the address is transferred in two bytes. If the first transfer (con-
taining the most significant address bits) matches the most-significant bits of the Slave
address, an interrupt will be generated on both halves of the address. If the second part of
the address does not match, the ICSTAT RXABORT bit is set, informing the interrupt han-
dler that the address was not a complete match.
In transmit mode, the ICCON must be updated on a byte-by-byte basis, because the
ICCON START bit must be set to 1 to initiate a byte transfer. This register also contains
bits that set the operating mode.
In Master mode, bus synchronization is handled in hardware. Addressing, which was han-
dled in hardware in Slave mode, is handled in software in Master mode. For example, the
R/W bit of a 7-bit address must be set in software; it is not overwritten by the state of the
R/W bit in the ICCON register.
Status bits in the ICSTAT register reports the precise state of the I
there are status bits reporting whether the current transfer is a Slave address or if a trans-
mit abort or receive data overrun has occurred.
9-4
2
C Module handles address comparison, shifts data into or out of the
Version 1.0
LH79524/LH79525 User's Guide
2
C Module ignores transfers not addressed
2
C Module. For example,
2
C Module
2
C Module do not

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