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LH79524/LH79525 User's Guide
Glossary
ECC
Error Correction Code. This code, appended to a packet or page of data, allows not only
detection of errors in the data stream, but correction of the errors as well.
ED
Endpoint Descriptor. A memory structure that describes the information necessary for the
USB Host Controller to communicate (via Transfer Descriptors) with a USB Client End-
point. An ED includes a Transfer Descriptor pointer.
Embedded SRAM
In the LH79524/LH79525, 16KB of on-chip SRAM. The LCD controller has access to an
internal frame buffer in embedded SRAM and an extension buffer in SDRAM for dual panel
or large displays. The core and DMA controller share the main system bus, providing
access to all external memory devices and the embedded SRAM frame buffer.
ENDEC
Encoder and Decoder
Endianness
Describes the bit, byte, or word sequence of data communication or storage, associating
the most significant or least significant end of a data sequence with the lowest address or
with the beginning of reception or transmission. See Big-endian and Little-endian.
Endpoint Address
The combination of a client Device Address and an Endpoint Number on the USB.
EOF
End Of Frame. The end of a USB-defined frame.
EMC
External Memory Controller. In the LH79524/LH79525, the EMC is an AHB slave block,
providing an interface between the AHB and external memory-mapped devices.
FIQ
Fast Interrupt request. FIQs are assigned in the VIC. FIQ interrupts are higher priority than
an IRQ. See IRQ.
Frame (USB)
A frame begins with a Start of Frame (SOF) token and is 1.0 ms +/- 0.25% in length.
GPIO
General Purpose Input and Output
Version 1.0
20-3
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