Figure 7-8. Typical Memory Connection Diagram - Sharp LH79524 User Manual

External Memory Controller
A[20:0]
nBLE3
nBLE2
nBLE1
nBLE0
7-8
nCS0
nOE
nCS1
nWE
nCS2

Figure 7-8. Typical Memory Connection Diagram

A[20:0]
nCE
nOE
2M × 32 BURST MASK ROM
A[15:0]
nCE
nOE
nWE
nUB
nLB
A[15:0]
nCE
nOE
nWE
nUB
nLB
64K × 16 SRAM, × 2
A[16:0]
nCE
nOE
nWE
A[16:0]
nCE
nOE
nWE
A[16:0]
nCE
nOE
nWE
A[16:0]
nCE
nOE
nWE
128K × 8 SRAM, × 4
Version 1.0
LH79524/LH79525 User's Guide
D[31:0]
Q[31:0]
D[31:16]
IO[15:0]
D[15:0]
IO[15:0]
D[31:24]
IO[7:0]
D[23:16]
IO[7:0]
D[15:8]
IO[7:0]
D[7:0]
IO[7:0]
LH79525-93