Table 10-5. Stat Register; Table 10-6. Stat Register Definitions; Status Register (Stat) - Sharp LH79524 User Manual

2
I S Converter

10.2.2.2 Status Register (STAT)

This register reports various I
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:9
8
7
6
5
4
3
2
1
0
10-16
2
31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO

Table 10-6. STAT Register Definitions

NAME
/// Reserved Reading returns 0. Write the reset value.
Master or Slave Mode Select (From SSP CTRL1:MS bit)
MS
1 = Device configured as slave
0 = Device configured as a master (default)
Receive FIFO Full (From SSP SR:RFF bit)
RFF
1 = The Receive FIFO is full
0 = The Receive FIFO is not full
Receive FIFO Empty
RFE
1 = The Receive FIFO is empty
0 = The Receive FIFO is not empty
Transmit FIFO Full
TFF
1 = The Transmit FIFO is full
0 = The Transmit FIFO is not full
Transmit FIFO Empty (From SSP SR:TFE bit)
TFE
1 = The Transmit FIFO is empty
0 = The Transmit FIFO is not empty
WS value for TX word Applies only to I
TXWS
1 = Next word written to SSP TX FIFO will have WS = 1
0 = Next word written to SSP TX FIFO will have WS = 0
WS value for RX word Applies only to I
RXWS
1 = Next word read from SSP RX FIFO will have WS = 1
0 = Next word read from SSP RX FIFO will have WS = 0
WS value at pin This status bit is a real-time report of WS value at the pin.
WS
Applies only to I
2
I S Loopback Mode Applies only to I
LBM
2
1 = Output of I
0 = Normal serial port operation enabled
S converter functions. All bits are read only.

Table 10-5. STAT Register

26 25 24 23 22
///
0 0 0 0 0
RO RO RO RO RO
10 9 8 7 6
MS RFF RFE
0 0 0 0 1
RO RO RO RO RO
0xFFFC8000 + 0x004
DESCRIPTION
2
S Transactions
2
S Converter connected to input of I
Version 1.0
LH79524/LH79525 User's Guide
21 20 19
0 0 0
RO RO RO RO
5 4 3
TFF TFE TXWS RXWS
0 1 0
RO RO RO RO
2
S Transactions
2
S Transactions
S Transactions
2
S Converter internally
18 17 16
0 0 0
RO RO
2 1 0
WS LBM
0 1 0
RO RO