Line Control Register (Uartlcr_H) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

16.3.2.7 Line Control Register (UARTLCR_H)

UARTLCR_H is the Line Control Register. This register is used to configure the UARTs.
The contents of the UARTLCR_H Register are not updated until transmission or reception
of the current character is complete. Table 16-21 is a truth table for the SPS, EPS, and
PEN bits of the UARTLCR_H Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:10
9
8
7
6:5
Table 16-19. UARTLCR_H Register
31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO
Table 16-20. UARTLCR_H Fields
NAME
/// Reserved Reading returns 0. Write the reset value.
Nine-bit Mode Enable Use this bit to enable Nine-bit Mode.
1 = Nine-bit Mode enabled; characters are tagged during transmission as ad-
9BIT
dress or data and checked during reception for address or data
0 = Nine-bit Mode disabled
Transmit Address This bit allows tagging characters in the UARTDR. Not
used and ignored if Nine-bit MODE ENABLE = 0.
During Nine-bit Mode (9BIT = 1):
ADDTX
1 = The next character written to UARTDR is tagged as an address. This bit is
automatically cleared when UARTDR is written.
0 = The next character written to UARTDR is tagged as data.
Stick Parity Select Bits [7], [2], and [1] work together to set up the parity. See
SPS
Table 16-21.
Word Length Indicates the number of data bits transmitted or received in a frame.
00 = 5 bits
WLEN
01 = 6 bits
10 = 7 bits
11 = 8 bits
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
RO RW RW RW
UART 0: 0xFFFC0000 + 0x02C
UART 1: 0xFFFC1000 + 0x02C
UART 2: 0xFFFC2000 + 0x02C
DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
UARTs
17 16
0 0
RO RO
1 0
0 0
RW RW
16-15