LH79524/LH79525 User's Guide
6.3.4.5 Specific Address 2 Bottom (SPECAD2BOT)
This register contains the least-significant bits of the destination address (bits [31:0]). Bit
zero indicates whether the address is multicast or unicast and corresponds to the least
significant bit of the first byte received.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:0
6.3.4.6 Specific Address 2 Top (SPECAD2TOP)
This register contains the most-significant bits of the destination address (bits [47:32]).
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:16
15:0
Table 6-84. SPECAD2BOT Register
31
30
29
28
27
0
0
0
0
0
RW
RW
RW
RW
RW
15
14
13
12
11
0
0
0
0
0
RW
RW
RW
RW
RW
Table 6-85. SPECAD2BOT Fields
NAME
Least Significant Destination Address Bits Least significant bits
SPECAD2BOT
of the destination address.
Table 6-86. SPECAD2TOP Register
31
30
29
28
27
0
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
11
0
0
0
0
0
RW
RW
RW
RW
RW
Table 6-87. SPECAD2TOP Fields
NAME
///
Reserved Reading returns 0. Write the reset value.
Most Significant Destination Address Bits The most significant
SPECAD2TOP
bits of the destination address.
26
25
24
23
SPECAD2BOT
0
0
0
0
RW
RW
RW
RW
10
9
8
7
SPECAD2BOT
0
0
0
0
RW
RW
RW
RW
0xFFFC7000 + 0xA0
FUNCTION
26
25
24
23
///
0
0
0
0
RO
RO
RO
RO
10
9
8
7
SPECAD2TOP
0
0
0
0
RW
RW
RW
RW
0xFFFC7000 + 0xA4
FUNCTION
Version 1.0
Ethernet MAC Controller
22
21
20
19
18
0
0
0
0
0
RW
RW
RW
RW
RW
6
5
4
3
2
0
0
0
0
0
RW
RW
RW
RW
RW
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
0
0
0
0
0
RW
RW
RW
RW
RW
17
16
0
0
RW
RW
1
0
0
0
RW
RW
17
16
0
0
RO
RO
1
0
0
0
RW
RW
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