Hardware Design - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

7.2.2 Hardware Design

Automatic address shifting makes hardware design much simpler. This section provides a
description and guide for hardware design and interfacing.
7.2.2.1 Address Connectivity
Rather than connecting different address pins to different memory devices depending on
the width, SoC address pin A0 always connects to device pin A0, SoC address pin A1 to
device pin A1, continuing through SoC pin A23 connecting to device pin A23.
7.2.2.1.1 Memory Banks of 8-bit or Non Byte-partitioned Memory Devices
For memory banks constructed from 8-bit or non byte-partitioned memory devices, it is
important that the Byte Lane State (BLS) bit is cleared to 0 within the respective memory
bank control register. This forces all nBLEx lines HIGH during a read access as the byte
lane selects are connected to the device write enables.
Figure 7-3 through Figure 7-5 show 8-bit memory being used to configure memory banks
that are 8, 16, and 32 bits wide. In each of these configurations, the nBLEx signals are
connected to write enable (nWE) inputs of each 8-bit memory. The nWE signal is not used.
For write transfers, the relevant nBLEx byte lane signals are asserted LOW, and steer
the data to the address bytes. For read transfers, all of the nBLEx lines are deasserted HIGH,
which enables the external bus to be defined for at least the width of the accessed memory.
7.2.2.1.2 Memory Banks of 16- or 32-bit Memory Devices
For memory banks constructed from 16- or 32-bit memory devices, it is important that
the Byte Lane Select (BLS) bit is set to 1 within the respective memory bank control reg-
ister. This asserts all nBLEx lines LOW during a read access as during a read all bytes
of the device must be selected to avoid un-driven byte lanes on the read data value. In the
case of 16- and 32-bit wide memory devices, byte select signals exist and these must be
appropriately controlled, as shown in Figure 7-6 and Figure 7-7.
Figure 7-8 shows a connection for a typical memory system with different data width
memory devices.
7.2.2.1.3 Address Connectivity, Address Right-justified
Figure 7-3 to Figure 7-8 show memory controller connection to static memory where the
address is right justified. Right justification reduces the number of address pins and keeps
the number of addresses constant, whether those addresses contain 8, 16, or 32 bits of data.
It's important to understand the difference between address signals, which are the actual
address signals and the address pins, which carry the signals to the external memory bus.
When addressing 8-bit memory, address signals A[23:0] are mapped in a 1:1 correspon-
dence with pins A[23:0], since transactions occur on byte boundaries. With 16-bit memory,
address signal A0 is not necessary since all transactions occur on half-word boundaries.
Thus, when the memory width is set to 16 bits, the address pins contain the right-justified
address signals. Signal A0 is not used; signal A1 appears on pin A0; signal A2 appears on
pin A1, and so on through signal A24 appearing on pin A23. With 32-bit memory, right-jus-
tification omits signals A0 and A1. So, for 32-bit memory, signal A2 appears on pin A0, and
signal A25 appears on pin A23.
Version 1.0
External Memory Controller
7-5