Table 17-6. Pmr Register; Table 17-7. Pmr Fields; Power Management Register (Pmr) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

17.2.2.2 Power Management Register (PMR)

This register is used for SUSPEND, RESUME, and RESET signalling, and for monitoring
USB Bus Reset status.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
TYPE
ADDR
BITS
32:8
7
6:4
3
2
1
0 ENABLE_SUSPEND
31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO
NAME
/// Reserved Reading returns 0. Write the reset value.
Start of Frame Update This bit allows software to instruct the USB Device to
wait for an SOF token from the time IN_PKT_RDY is set before sending the
packet. If an IN token is received before an SOF token, a zero length data pack-
SOF_UPDATE
et is sent. This bit is only used by endpoints performing Isochronous transfers.
1 = Wait for SOF token before sending the pending packet
0 = Do not wait for the SOF token before sending packets
/// Reserved Reading returns 0. Write the reset value.
USB RESET The USB block programs this bit to 1 when RESET signalling
is received from the Host. This bit remains 1 as long as RESET persists on
the USB bus.
USB_RESET
1 = A RESET signal is asserted on the USB bus
0 = No RESET signal is asserted
UC RESUME Software programs a 1 to this bit for not less than 10 ms, nor
more than 15 ms to initiate RESUME signalling.
UC_RESUME
1 = Initiate RESUME signalling (must be 10 ms to 15 ms)
0 = Normal operation
SUSPEND Mode The USB block programs this bit to 1 when the Host
sends SUSPEND signalling to the SoC.
SUSPEND_MODE
1 = USB in SUSPEND mode
0 = USB not in SUSPEND mode
SUSPEND Enable The software programs this bit to 1 to enable the
SUSPEND mode. If this bit is zero, the device will not enter SUSPEND mode.
1 = Enable SUSPEND mode
0 = Disable SUSPEND mode (Default)

Table 17-6. PMR Register

26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
RO RO RO RW
0xFFFF5000 + 0x004

Table 17-7. PMR Fields

FUNCTION
Version 1.0
Universal Serial Bus Device
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
///
0 0 0 1 0
RO RO RO RO RW
17 16
0 0
RO RO
1 0
0 0
RO RW
17-11