Table 16-6. Uartrsr/Uartecr Register (Write Operations); Table 16-7. Uartrsr/Uartecr Fields (Write Operations); Table 16-5. Nine-Bit Mode/Parity Bit Table; Receive Status/Error Clear Register (Uartrsr/Uartecr) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
REGISTER:BIT
UARTLCR_H:
9BIT
0
0
1
1

16.3.2.2 Receive Status/Error Clear Register (UARTRSR/UARTECR)

UARTRSR/UARTECR is the Receive Status Register/Error Clear Register. If the status is
read from this register, the status bits in this register correspond to the status bits of the
last word read from the UARTDR Register (see Section 16.3.2.1). The status information
for overrun is set immediately when an overrun condition occurs.
A write to the UARTECR Register clears the Framing, Parity/address Received, Break,
and Overrun Errors. All bits clear to 0 on System Reset.
NOTE: The received data character must be read first from UARTDR before reading the error status
Table 16-6 and Table 16-7 describe the UARTRSR/UARTECR Register for Write operations.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:8
7:0

Table 16-5. Nine-bit Mode/Parity Bit Table

UARTDR:
PEAR
The parity of the received data character matches the parity selected as de-
0 fined by the EPS and SPS bits in the UARTLCR_H register. In FIFO mode,
this error is associated with the character at the top of the FIFO.
The parity of the received data character does not match the parity selected
1 as defined by the EPS and SPS bits in the UARTLCR_H register. In FIFO
mode, this error is associated with the character at the top of the FIFO.
0 The received character is data.
1 The received character is an address.
associated with that data character from UARTRSR. This read sequence cannot be reversed
because the Status Register, UARTRSR, is updated only when a read occurs from the Data Register,
UARTDR. However, the status information can also be obtained by reading the UARTDR Register.

Table 16-6. UARTRSR/UARTECR Register (Write Operations)

31 30 29 28
0 0 0 0
RO RO RO RO RO
15 14 13 12
///
0 0 0 0
RO RO RO RO RO

Table 16-7. UARTRSR/UARTECR Fields (Write Operations)

/// Reserved Reading returns 0. Write the reset value.
Error Clear A Write to this register clears the Framing, Break, Parity/Address
EC
Received, and Overrun Errors. The data value is not important.
27 26 25 24 23
///
0 0 0 0 0
RO RO RO RO
11 10 9 8 7
0 0 0 0 0
RO RO RO WO
UART 0: 0xFFFC0000 + 0x004
UART 1: 0xFFFC1000 + 0x004
UART 2: 0xFFFC2000 + 0x004
DESCRIPTION
Version 1.0
MEANING
22 21 20 19
0 0 0 0
RO RO RO RO RO
6 5 4 3
EC
0 0 0 0
WO WO WO WO WO
UARTs
18 17 16
0 0 0
RO RO
2 1 0
0 0 0
WO WO
16-9