Setup - Sharp LH79524 User Manual

Ethernet MAC Controller

6.1.1.1 Setup

Prior to use, software must allocate system resources, initialize, and program the EMAC.
Receive and Transmit buffers must be allocated in system memory. Software must also
load the MAC address into Specific Address Register 1, initialize the Buffer Pointer Queue
Registers, set up the network parameters in the Network Control Register and Network
Configuration Register, and enable any applicable interrupts in the Interrupt Enable Reg-
ister. Once these housekeeping details have been completed, the transmitter and receiver
can be enabled.
6.1.1.2 Statistics
As network communication transpires, statistics are maintained in the set of Statistics
Registers. These registers can be interrogated at any time by software. Upon reading,
the count value is reset to zero. If the registers are not read before reaching the maximum
count value, they will 'stick' at all ones, indicating an overflow has occurred since the reg-
ister was last read.
6.1.1.3 Detailed Descriptions
The following sections provide detailed information about the functional blocks within the
EMAC, buffers, DMA, and specific operation.
6.1.2 Memory Interface
Ethernet frame data is stored in LH79524/LH79525 system memory. It is transferred to
and from the Ethernet MAC through the DMA interface. All transfers are 32-bit words and
may be single accesses, or bursts of 2, 3, or 4 words (transfers for the LH79525 are auto-
matically parsed into two 16-bit transfers to accommodate its 16-bit data bus). Four-word
bursts are the default data transfer, however single accesses, or bursts fewer than four
words may be used to transfer data at the beginning or the end of a buffer. Burst accesses
do not cross 16-byte boundaries.
6.1.2.1 FIFO
The receive and transmit FIFO depths are both set to 16 entries.
Data is typically transferred to and from the onboard FIFOs in bursts of four words. For
receive, a bus request is asserted when the FIFO contains four words and has space for
more. For transmit, a bus request is generated when there is space for four words, or when
there is space for two words if the next transfer is to be only one or two words.
6.1.2.2 Receive Buffers
As each valid frame is received, it is stored in a 128-byte receive buffer. The start location
for each receive buffer is stored in memory in a list of receive buffer descriptors at a loca-
tion pointed to by the Receive Buffer Queue Pointer register (RXBQP). The receive buffer
start location is a word address which can be offset by up to three bytes depending on the
value written to the Network Configuration register (NETCONFIG:RXBUFOS). If the start
location of the buffer is offset, the available length of the first buffer of a frame is reduced
by the corresponding number of bytes.
6-4 Version 1.0
LH79524/LH79525 User's Guide