Adc Register Definitions; High Word Register; Table 23-2. Hw Register; Table 23-3. Hw Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

23.3.2 ADC Register Definitions

23.3.2.1 High Word Register

HW is the High Word Register. This Read Only status register shows the contents of the
current conversion's high word in the control bank. There is a one-to-one correspondence
between the contents of the control bank high word and the contents of this register for the
current conversion in progress.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:7 SETTIME
6:3
2
1:0
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
SETTIME
0 0 0 0 0
R R R R R

Table 23-3. HW Register Definitions

NAME
/// Reserved Read as zero
Number of Clock Cycles Number of clock cycles that the ADC allows for the
input signal to settle to within required accuracy before beginning conversion.
Used with bits [10:8] of the PC Register to set the acquire time in clock cycles
(see Section 23.3.2.5).
For example, Frequency In (ƒIN)
2 MHz (500 ns period)
PC[10:8] = 010 (i.e., divide ƒIN by 4)
HW[15:6] = 000100000 (i.e., 32 cycles)
Therefore, acquire time is 500 ns × 4 × 32 = 64 µs
In+ Mux Determines the signal connected to the positive input of the ADC.
INP
See Table 23-4.
In- Mux Determines the signal connected to the negative input of the ADC.
INM
0 = Ref- (output of the Ref- Mux)
1 = GND
Ref+ Mux Determines the signal connected to the positive reference of the ADC.
00 = VREF+ (positive terminal of the internal bandgap reference)
RefP
01 = AN0 (UL/X+)
10 = AN2 (LL/ Y+)
11 = AN8
Analog-to-Digital Converter/Brownout Detector

Table 23-2. HW Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
0 0 0 0
R R R R
0xFFFC3000 + 0x00
DESCRIPTION
6/25/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
INP INM
0 0 0 0 0
R R R R R
17 16
0 0
R R
1 0
RefP
0 0
R R
23-9