Reset Status Register; Table 9-11. Resetstatus Register; Table 9-12. Resetstatus Register Definitions - Sharp Blue Treak LH75400 User Manual

Reset, Clock, and Power Controller

9.3.2.5 Reset Status Register

ResetStatus is the Reset Status Register. This Read Only register provides the reset sta-
tus of the device. It contains the external reset status and the WDT timeout reset status.
At external reset, the EXT bit is set and the WDTO bit is cleared. At WDT timeout, only the
WDTO bit is set. The EXT and WDTO bits remain set until they are cleared by the Reset
Status Clear operation.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS FIELD NAME
31:2
1
0
9-10

Table 9-11. ResetStatus Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 9-12. ResetStatus Register Definitions

/// Reserved Writing to these bits has no effect.
WDT Timeout
WDTO
0 = No WDT timeout has occurred since the flag was last cleared.
1 = WDT timeout has occurred.
External Reset
EXT
0 = No external reset has occurred since the flag was last cleared.
1 = External reset has occurred.
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
///
0 0 0 0
R R R R R
10 9 8 7
—
0 0 0 0
R R R R R
0xFFFE2000 + 0x10
DESCRIPTION
7/15/03
21 20 19 18
0 0 0 0 0
R R R R
6 5 4 3 2
0 0 0 0 0
R R R R
17 16
0 0
R R
1 0
EXT
0 1
R R