Interrupt Status/Clear; Table 17-10. Stat/Eoi Register (Write Operations); Table 17-11. Stat/Eoi Register Definitions (Write Operations); Table 17-12. Stat/Eoi Register (Read Operations) - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

17.3.2.5 Interrupt Status/Clear

STAT/EOI is the Interrupt Status/Clear Register. The write location is a virtual address with
no physical storage element. A write to this location clears the RTCINTR interrupt line and the
corresponding status bit. A read from bit 0 returns the value of RTCINTR.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
NOTE: The reset value of this register's bits is indeterminate.
BITS
31:0
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
NOTE: The reset value of this register's bits is indeterminate.

Table 17-10. STAT/EOI Register (Write Operations)

31 30 29 28 27
— — — — —
W W W W W
15 14 13 12 11
— — — — —
W W W W W

Table 17-11. STAT/EOI Register Definitions (Write Operations)

NAME
End Of Interrupt A write to this register clears RTCINTR, regardless of the
RTCEOI
data value written.

Table 17-12. STAT/EOI Register (Read Operations)

31 30 29 28 27
— — — — —
R R R R
15 14 13 12 11
— — — — —
R R R R

Table 17-13. STAT/EOI Register Definitions (Read Operations)

BITS NAME
31:1 ///
0 RTCINTR
26 25 24 23
RTCEOI
— — — —
W W W W
10 9 8 7
RTCEOI
— — — —
W W W W
0xFFFE0000 + 0x10
DESCRIPTION
26 25 24 23
///
— — — —
R R R R R
10 9 8 7
///
— — — —
R R R R R
0xFFFE0000 + 0x10
DESCRIPTION
Reserved Unpredictable when read.
Interrupt Status
1 = RTCINTR interrupt is asserted.
0 = RTCINTR interrupt is not asserted.
6/17/03
Real-Time Clock
22 21 20 19 18
— — — — —
W W W W W
6 5 4 3 2
— — — — —
W W W W W
22 21 20 19 18
— — — — —
R R R R R
6 5 4 3 2
— — — — —
R R R R R
17 16
— —
W W
1 0
— —
W W
17 16
— —
R R
1 0
— —
R RW
17-7