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LH75400/01/10/11 (Preliminary) User's Guide
18.5.3 SSP Interrupts
The SSP can assert four interrupts:
• SSPRXINTR — SSP Receive FIFO Service Interrupt request, locally maskable
• SSPTXINTR — SSP Transmit FIFO Service Interrupt request, locally maskable
• SSPRORINTR — SSP Receive Overrun Interrupt request, locally maskable
• SSPRXTOINTR — SSP Receive FIFO Timeout Interrupt request.
The first three interrupts can be enabled or disabled by changing the mask bits in Control
Register 1. Setting the appropriate mask bit HIGH enables the interrupt. The fourth inter-
rupt, SSPRXTOINTR SSP, is not locally maskable and should be masked using the Vec-
tored Interrupt Controller IntEnable Register (see Section 10.2.2.5). All four interrupts are
combined into a single interrupt: SSPINTR.
If the Receive Timeout function is not required, disable it by writing the value 0x0000 to the
RXTO Register. Writing any value to this register clears the current SSPRXTOINTR interrupt.
Provision of the individual outputs as well as a combined interrupt output, allows use of
either a global ISR or modular device drivers to handle interrupts from the SSP.
The status of the four individual interrupt sources can be read from the IIR Register.
18.5.3.1 Receive Interrupt
SSPRXINTR is the Receive Interrupt. This interrupt is asserted when there are four or more
valid entries in the receive FIFO. The interrupt is cleared by reading the receive FIFO until
there are three or fewer entries.
18.5.3.2 Transmit Interrupt
SSPTXINTR is the Transmit Interrupt. This interrupt is asserted when the FIFO is less than
or equal to half full (when there is space for four or more entries). The interrupt is cleared
when there are five or more entries in the transmit FIFO.
This interrupt is not qualified with the Synchronous Serial Port Enable bit (bit [4]) in Control
Register 1, which allows operation in one of two ways. Data can be written to the transmit
FIFO prior to enabling the SSP and the interrupts. Alternatively, the SSP and interrupts can
be enabled so that data can be written to the transmit FIFO by an ISR. For more information
about Control Register 1, see Section 18.5.2.2.
NOTE: The SSPTXINTR interrupt is always set if the Synchronous Serial Port Enable bit in Control Register
18.5.3.3 Receive Overrun Interrupt
SSPRORINTR is the Receive Overrun Interrupt. This interrupt is asserted when the FIFO
is already full and an additional data frame is received, causing an overrun of the FIFO.
Data is over-written in the Shift Register, but not the FIFO.
1 is not set.
6/17/03
Synchronous Serial Port
18-19
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