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Color Liquid Crystal Display Controller
13.5 Timing Waveforms
This section describes typical output waveform diagrams for the CLCDC and the HRTFTC.
13.5.1 STN Horizontal Timing
Figure 13-2 shows typical horizontal timing waveforms for STN panels. In this figure, the
CLCDC Clock (an input to the CLCDC) is scaled within the CLCDC and used to produce
the LCDDCLK output. Programmable registers in the CLCDC set the timings (in terms of
LCDDCLK pulses) to produce the other signals that control an STN display.
For example, Figure 13-2 shows that the duration of the LCDLP signal is controlled by
Timing0:HSW (the HSW bit field in the Timing0 Register). Figure 13-2 also shows that the
polarity of the LCDLP signal is set by Timing2:IHS.
13.5.2 STN Vertical Timing
Figure 13-3 shows typical vertical timing waveforms for STN panels.
13.5.3 TFT Horizontal Timing
Figure 13-4 shows typical horizontal timing waveforms for TFT panels.
13.5.4 TFT Vertical Timing
Figure 13-5 shows typical vertical timing waveforms for TFT panels.
13.5.5 HR-TFT Horizontal Timing Waveforms
Figure 13-6 shows typical horizontal timing waveforms for HR-TFT panels. The HRTFTC
delays the normal TFT timing to accommodate HR-TFT panels.
13.5.6 HR-TFT Vertical Timing Waveforms
Figure 13-7 shows typical vertical timing waveforms for HR-TFT panels.
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LH75400/01/10/11 (Preliminary) User's Guide
7/15/03
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