Omron CS1W-MC221 - 02-2008 Operation Manual page 647

Control Bit/Flag Timing Charts
23. Cycle Start Bit, Pause Bit, M Code Reset Bit, and M Code Output
Cycle Start Bit
Pause Bit
M Code Reset Bit
M Code
Operation
The program is paused when the Pause Bit is turned ON, but the M code is not cleared. M code M10 is not
cleared by the M Code Reset Bit because program execution is paused.
24. Cycle Start Bit, Pause Bit, M Code Reset Bit, and M Code Output
Cycle Start Bit
Pause Bit
M Code Reset Bit
M Code
Operation
If the Pause Bit and M Code Reset Bit are turned ON at the same time, the Pause Bit becomes valid. Program
execution is paused, but the M code is not cleared. When the program is restarted, the M code will be output
because it was ON originally.
25. Cycle Start Bit, Forced Block End Bit, and M Code Output
Cycle Start Bit
Forced Block End Bit
M Code
Operation
The Forced Block End Bit is turned ON while the Unit is standing by for an M code reset, cancelling the block.
620
10
100
Appendix E