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timing requirements for the HOLD/HOLDA cycles
NO
NO.
1
t
su(HOLDH-CKO1H)
2
t
h(CKO1H-HOLDL)
†
HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.
Thus, HOLD can be an asynchronous input.
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles
(see Figure 27)
NO
NO.
3
t
d(HOLDL-BHZ)
4
t
d(BHZ-HOLDAL)
5
t
d(HOLDH-HOLDAH)
6
t
d(CKO1H-HOLDAL)
7
t
d(CKO1H-BHZ)
8
t
d(CKO1H-BLZ)
9
t
d(HOLDH-BLZ)
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§
All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write
with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
¶
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
DSP Owns Bus
CLKOUT1
HOLD
HOLDA
†
EMIF Bus
†
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
HOLD/HOLDA TIMING
Setup time, HOLD high before CLKOUT1 high
Hold time, HOLD low after CLKOUT1 high
PARAMETER
PARAMETER
Delay time, HOLD low to EMIF Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to HOLDA high
Delay time, CLKOUT1 high to HOLDA valid
Delay time, CLKOUT1 high to EMIF Bus high impedance
Delay time, CLKOUT1 high to EMIF Bus low impedance
Delay time, HOLD high to EMIF Bus low impedance
4
3
2
1
6
7
C62x
Figure 27. HOLD/HOLDA Timing
POST OFFICE BOX 1443
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
†
(see Figure 27)
¶
¶
External Requester
9
2
1
Ext Req
•
HOUSTON, TEXAS 77251--1443
TMS320C6201
- -200
MIN
MAX
1
4
- -200
MIN
MAX
§
4P
P
2P
4P
7P
1
8
3
11
3
11
3P
6P
DSP Owns Bus
5
6
8
C62x
UNIT
UNIT
ns
ns
‡
UNIT
UNIT
ns
ns
ns
ns
ns
ns
ns
43
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