Synchronous Dram Timing - Texas Instruments TMS320C6201 Manual

Fixed-point digital signal processor
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timing requirements for synchronous DRAM cycles (see Figure 21)
NO.
NO
7
t
su(EDV-SDCLKH)
8
t
h(SDCLKH-EDV)
switching characteristics over recommended operating conditions for synchronous DRAM
cycles
(see Figure 21- -Figure 26)
NO.
NO
1
t
osu(CEV-SDCLKH)
2
t
oh(SDCLKH-CEV)
3
t
osu(BEV-SDCLKH)
4
t
oh(SDCLKH-BEIV)
5
t
osu(EAV-SDCLKH)
6
t
oh(SDCLKH-EAIV)
9
t
osu(SDCAS-SDCLKH)
10
t
oh(SDCLKH-SDCAS)
11
t
osu(EDV-SDCLKH)
12
t
oh(SDCLKH-EDIV)
13
t
osu(SDWE-SDCLKH)
14
t
oh(SDCLKH-SDWE)
15
t
osu(SDA10V-SDCLKH)
16
t
oh(SDCLKH-SDA10IV)
17
t
osu(SDRAS-SDCLKH)
18
t
oh(SDCLKH-SDRAS)
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.

SYNCHRONOUS DRAM TIMING

Setup time, read EDx valid before SDCLK high
Hold time, read EDx valid after SDCLK high
PARAMETER
PARAMETER
Output setup time, CEx valid before SDCLK high
Output hold time, CEx valid after SDCLK high
Output setup time, BEx valid before SDCLK high
Output hold time, BEx invalid after SDCLK high
Output setup time, EAx valid before SDCLK high
Output hold time, EAx invalid after SDCLK high
Output setup time, SDCAS valid before SDCLK high
Output hold time, SDCAS valid after SDCLK high
Output setup time, EDx valid before SDCLK high
Output hold time, EDx invalid after SDCLK high
Output setup time, SDWE valid before SDCLK high
Output hold time, SDWE valid after SDCLK high
Output setup time, SDA10 valid before SDCLK high
Output hold time, SDA10 invalid after SDCLK high
Output setup time, SDRAS valid before SDCLK high
Output hold time, SDRAS valid after SDCLK high
POST OFFICE BOX 1443
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
HOUSTON, TEXAS 77251--1443
TMS320C6201
- -200
UNIT
UNIT
MIN
MAX
0.5
ns
3
ns
- -200
UNIT
UNIT
MIN
MAX
1.5P -- 3.5
ns
0.5P -- 1
ns
1.5P -- 3.5
ns
0.5P -- 1
ns
1.5P -- 3.5
ns
0.5P -- 1
ns
1.5P -- 3.5
ns
0.5P -- 1
ns
1.5P -- 3.5
ns
0.5P -- 1
ns
1.5P -- 3.5
ns
0.5P -- 1
ns
1.5P -- 3.5
ns
0.5P -- 1
ns
1.5P -- 3.5
ns
0.5P -- 1
ns
39

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