Advisory; Cache During Emulation With Extremely Slow External Memory - Texas Instruments TMS320C6201 Errata

TMS320C6201 Silicon Errata

Advisory 3.1.9

Revision(s) Affected:
Details:
Workaround:
Alternative: If a 64M-bit SDRAM is located in CE3, avoid using the last 1K byte in the CE3
memory map (0x03FFFC00).

Cache During Emulation With Extremely Slow External Memory

3.1, 3.0, 2.1, and 2.0
If a program requests fetch packet "A" followed immediately by fetch packet "B", and all of the
following four conditions are true:
1. A and B are separated by a multiple of 64K in memory (i.e., they will occupy the same
cache frame)
2. B is currently located in cache
3. You are using the emulator to single-step through the branch from A to B
4. The code is running off of an extremely slow external memory that transfers one 32-bit
word every 8000 or more CPU clock cycles (CPU running at 200 MHz)
Then A will be registered as a "miss" and B will be registered as a "hit". B will not be reloaded
into cache, and A will be executed twice. This condition is extremely rare because B has to be
in cache memory, and must be the next fetch packet requested after A (which is not in cache
memory). In addition, this problem only occurs if you single-step through the branch from A to
B using the emulator, and if the code is located in an extremely slow external memory.
(Internal reference number C630283)
Do not single-step through the branch from A to B if the above conditions are true.
Do not use an extremely slow external memory (transfers one 32-bit word every 8000
or more CPU clock cycles) if conditions 1, 2, and 3 are true.
SPRZ153
11