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Texas Instruments TMS320C6000 Series Manuals
Manuals and User Guides for Texas Instruments TMS320C6000 Series. We have
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Texas Instruments TMS320C6000 Series manual available for free PDF download: Reference Manual
Texas Instruments TMS320C6000 Series Reference Manual (391 pages)
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 1.52 MB
Table of Contents
Table of Contents
9
Introduction
20
1.1 TMS320 Family Overview
21
History of TMS320 Dsps
21
Typical Applications for the TMS320 Family
21
Typical Applications for the TMS320 Dsps
22
1.2 Overview of the Tms320C6X Generation of Digital Signal Processors
23
1.3 Features and Options of the Tms320C62X/C67X
24
1.4 Tms320C62X/C67X Architecture
26
Peripherals
26
Tms320C62X/C67X Block Diagram
26
Control Registers
27
Tms320C62X CPU Data Paths
30
Tms320C67X CPU Data Paths
31
Storage Scheme for 40-Bit Data in a Register Pair
33
Functional Units and Operations Performed
34
Addressing Mode Register (AMR)
37
Addressing Mode Register (AMR) Mode Select Field Encoding
37
Block Size Calculations
38
Control Status Register (CSR)
39
Control Status Register Field Descriptions
39
E1 Phase Program Counter (PCE1)
40
Control Register File Extensions
41
Floating-Point Adder Configuration Register (FADCR)
42
Floating-Point Adder Configuration Register Field Descriptions
43
Floating-Point Auxiliary Configuration Register (FAUCR)
44
Floating-Point Auxiliary Configuration Register Field Descriptions
45
Floating-Point Multiplier Configuration Register (FMCR)
46
Floating-Point Multiplier Configuration Register Field Descriptions
47
Fixed-Point Instruction Operation and Execution Notations
49
Functional Unit to Instruction Mapping
52
Functional Unit to Instruction Mapping
53
Tms320C62X/C67X Opcode Map Symbol Definitions
56
Tms320C62X/C67X Opcode Map
57
Delay Slot and Functional Unit Latency Summary
59
Basic Format of a Fetch Packet
60
Registers that Can be Tested by Conditional Operations
63
Examples of the Detectability of Write Conflicts by the Assembler
67
Indirect Address Generation for Load/Store
70
Relationships between Operands, Operand Size, Signed/Unsigned, Functional
73
Units, and Opfields for Example Instruction (ADD)
73
Program Counter Values for Example Branch Using a Displacement
88
Program Counter Values for Example Branch Using a Register
90
Program Counter Values for B IRP
92
Program Counter Values for B NRP
94
Data Types Supported by Loads
114
Address Generator Options
114
Data Types Supported by Loads
119
Register Addresses for Accessing the Control Registers
134
Data Types Supported by Stores
170
Address Generator Options
170
Data Types Supported by Stores
174
Floating-Point Instruction Operation and Execution Notations
187
IEEE Floating-Point Notations
192
Single-Precision Floating-Point Fields
193
Special Single-Precision Values
193
Double-Precision Floating-Point Fields
194
Hex and Decimal Representation for Selected Single-Precision Values
194
Special Double-Precision Values
195
Hex and Decimal Representation for Selected Double-Precision Values
195
Delay Slot and Functional Unit Latency Summary
196
Address Generator Options
237
Tms320C67X Pipeline
268
Pipeline Operation Overview 6
268
Fetch
269
Fixed-Point Pipeline Stages
269
Fetch Phases of the Pipeline
270
Decode
271
Decode Phases of the Pipeline
271
Execute
272
Execute Phases of the Pipeline and Functional Block Diagram of the Tms320C62X
272
Summary of Pipeline Operation 6
273
Fixed-Point Pipeline Phases
273
Pipeline Operation: One Execute Packet Per Fetch Packet
273
Operations Occurring During Fixed-Point Pipeline Phases
274
Functional Block Diagram of Tms320C62X Based on Pipeline Phases
275
5.2 Pipeline Execution of Instruction Types
278
Execution Stage Length Description for each Instruction Type
278
Single-Cycle Instruction Phases
279
Single-Cycle Execution Block Diagram
279
Multiply Instruction Phases
279
Multiply Execution Block Diagram
280
Store Instruction Phases
280
Store Execution Block Diagram
281
Load Instruction Phases
282
Load Execution Block Diagram
282
Branch Instruction Phases
283
Branch Execution Block Diagram
284
Pipeline Operation: Fetch Packets with Different Numbers of Execute Packets
286
Multicycle NOP in an Execute Packet
287
Branching and Multicycle Nops
288
Pipeline Phases Used During Memory Accesses
289
Program Memory Accesses Versus Data Load Accesses
289
Program and Data Memory Stalls
290
Loads in Pipeline from Example
292
Floating-Point Pipeline Stages
294
Fetch Phases of the Pipeline
295
Decode Phases of the Pipeline
296
Execute Phases of the Pipeline and Functional Block Diagram of the Tms320C67X
297
Pipeline Operation: One Execute Packet Per Fetch Packet
298
Floating-Point Pipeline Phases
298
Operations Occurring During Floating-Point Pipeline Phases
299
Functional Block Diagram of Tms320C67X Based on Pipeline Phases
302
Execution Stage Length Description for each Instruction Type
305
6.3 Functional Unit Hazards
312
S-Unit Hazards
313
Single-Cycle .S-Unit Instruction Hazards
313
DP Compare .S-Unit Instruction Hazards
314
Branch .S-Unit Instruction Hazards
316
M-Unit Hazards
317
16 Multiply .M-Unit Instruction Hazards
317
MPYI .M-Unit Instruction Hazards
319
MPYID .M-Unit Instruction Hazards
320
MPYDP .M-Unit Instruction Hazards
321
L-Unit Hazards
322
Single-Cycle .L-Unit Instruction Hazards
322
INTDP .L-Unit Instruction Hazards
324
ADDDP/SUBDP .L-Unit Instruction Hazards
325
D-Unit Instruction Hazards
326
Load .D-Unit Instruction Hazards
326
Store .D-Unit Instruction Hazards
327
Single-Cycle .D-Unit Instruction Hazards
328
LDDW Instruction with Long Write Instruction Hazards
329
Single-Cycle Instructions
330
Single-Cycle Instruction Phases
330
Single-Cycle Execution Block Diagram
330
Single-Cycle Execution
330
16-Bit Multiply Instructions 6
331
Multiply Instruction Phases
331
Multiply Execution Block Diagram
331
16-Bit Multiply Execution
331
Store Instructions
332
Store Instruction Phases
332
Store Execution
332
Store Execution Block Diagram
333
Load Instructions
334
Load Instruction Phases
334
Load Execution
334
Load Execution Block Diagram
335
Branch Instructions
336
Branch Instruction Phases
336
Branch Execution
336
Branch Execution Block Diagram
337
2-Cycle DP Instructions
338
6.3.11 4-Cycle Instructions
339
INTDP Instruction 6
339
DP Compare Instructions 6
340
INTDP Instruction Phases
340
DP Compare Instruction Phases
340
INTDP Execution
340
DP Compare Execution
340
ADDDP/SUBDP Instructions 6
341
ADDDP/SUBDP Instruction Phases
341
ADDDP/SUBDP Execution
341
MPYI Instructions 6
342
MPYID Instructions 6
342
MPYI Instruction Phases
342
MPYI Execution
342
MPYID Execution
342
MPYDP Instructions 6
343
MPYID Instruction Phases
343
MPYDP Instruction Phases
343
MPYDP Execution
343
6.4 Performance Considerations
344
Pipeline Operation with Multiple Execute Packets in a Fetch Packet
344
Pipeline Operation: Fetch Packets with Different Numbers of Execute Packets
345
Multicycle Nops
346
Multicycle NOP in an Execute Packet
346
Branching and Multicycle Nops
347
Memory Considerations
348
Pipeline Phases Used During Memory Accesses
348
Program Memory Accesses Versus Data Load Accesses
348
Program and Data Memory Stalls
349
Loads in Pipeline from Example
351
Interrupt Service Table
356
Interrupt Service Fetch Packet
357
IST with Branch to Additional Interrupt Service Code Located Outside the ist
358
Interrupt Service Table Pointer (ISTP)
359
Interrupt Flag Register (IFR)
365
Interrupt Set Register (ISR)
366
Interrupt Clear Register (ICR)
366
NMI Return Pointer (NRP)
367
Interrupt Return Pointer (IRP)
368
Tms320C62X Nonreset Interrupt Detection and Processing: Pipeline Operation
370
Tms320C67X Nonreset Interrupt Detection and Processing: Pipeline Operation
371
RESET Interrupt Detection and Processing: Pipeline Operation
373
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