Reset Timing - Texas Instruments TMS320C6201 Manual

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
timing requirements for reset (see Figure 28)
NO. NO
1 1 t t
w(RST) w(RST)
†
This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.
‡
This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may
need up to 250 μs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted
to ensure proper device operation. See the Clock PLL section for PLL lock times.
switching characteristics over recommended operating conditions during reset
NO. NO
2 t
R(RST)
3 t
d(CKO1H-CKO2IV)
4 t
d(CKO1H-CKO2V)
5 t
d(CKO1H-SDCLKIV)
6 t
d(CKO1H-SDCLKV)
7 t
d(CKO1H-SSCKIV)
8 t
d(CKO1H-SSCKV)
9 t
d(CKO1H-LOWIV)
10 t
d(CKO1H-LOWV)
11 t
d(CKO1H-HIGHIV)
12 t
d(CKO1H-HIGHV)
13 t
d(CKO1H-ZHZ)
14 t
d(CKO1H-ZV)
§
Low group consists of:
High group consists of:
Z group consists of:
¶
HRDY is gated by input HCS.
If HCS = 0 at device reset, HRDY belongs to the high group.
If HCS = 1 at device reset, HRDY belongs to the low group.
44

RESET TIMING

Width of the RESET pulse (PLL stable)
Width of the RESET pulse (PLL needs to sync up)
PARAMETER PARAMETER
Response time to change of value in RESET signal
Delay time, CLKOUT1 high to CLKOUT2 invalid
Delay time, CLKOUT1 high to CLKOUT2 valid
Delay time, CLKOUT1 high to SDCLK invalid
Delay time, CLKOUT1 high to SDCLK valid
Delay time, CLKOUT1 high to SSCLK invalid
Delay time, CLKOUT1 high to SSCLK valid
Delay time, CLKOUT1 high to low group invalid
Delay time, CLKOUT1 high to low group valid
Delay time, CLKOUT1 high to high group invalid
Delay time, CLKOUT1 high to high group valid
Delay time, CLKOUT1 high to Z group high impedance
Delay time, CLKOUT1 high to Z group valid
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
HINT
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
POST OFFICE BOX 1443
†
‡
•
HOUSTON, TEXAS 77251--1443
- -200
UNIT UNIT
MIN MAX
CLKOUT1
10
cycles
250
μs
§¶
(see Figure 28)
- -200
UNIT UNIT
MIN MAX
CLKOUT1
2
cycles
--1 ns
10 ns
--1 ns
10 ns
--1 ns
10 ns
--1 ns
10 ns
--1 ns
10 ns
--1 ns
10 ns