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PIN NO.
SIGNAL
SIGNAL
NAME
GJC
CLKIN
C10
CLKOUT1
AF22
CLKOUT2
AF20
CLKMODE1
C6
CLKMODE0
C5
PLLFREQ3
A9
PLLFREQ2
D11
PLLFREQ1
B10
‡
PLLV
D12
‡
PLLG
C12
PLLF
A11
TMS
L3
TDO
W2
TDI
R4
TCK
R3
TRST
T1
EMU1
Y1
EMU0
W3
RESET
K2
NMI
L2
EXT_INT7
U3
EXT_INT6
V2
EXT_INT5
W1
EXT_INT4
U4
IACK
Y2
INUM3
AA1
INUM2
W4
INUM1
AA2
INUM0
AB1
LENDIAN
H3
PD
D3
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
‡
PLLV and PLLG are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.
§
A = Analog Signal (PLL Filter)
¶
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-kΩ resistor.
Signal Descriptions
†
†
TYPE
TYPE
GJL
CLOCK/PLL
B9
I
Clock Input
AC18
O
Clock output at full device speed
AC16
O
Clock output at half of device speed
Clock mode selects
D8
Selects whether the CPU clock frequency = input clock frequency x4 or x1
Selects whether the CPU clock frequency = input clock frequency x4 or x1
-
-
I
I
For more details on the GJC and GJL CLKMODE pins and the PLL multiply factors,
C7
see the Clock PLL section of this data sheet.
A9
PLL frequency range (3, 2, and 1)
PLL frequency range (3, 2, and 1)
D11
I
I
The target range for CLKOUT1 frequency is determined by the 3-bit value of the
The target range for CLKOUT1 frequency is determined by the 3-bit value of the
-
-
B10
PLLFREQ pins.
§
B11
A
PLL analog V
§
C12
A
PLL analog GND connection for the low-pass filter
§
D12
A
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
L3
I
JTAG test port mode select (features an internal pullup)
U4
O/Z
JTAG test port data out
T2
I
JTAG test port data in (features an internal pullup)
R3
I
JTAG test port clock
R4
I
JTAG test port reset (features an internal pulldown)
V3
I/O/Z
Emulation pin 1, pullup with a dedicated 20-kΩ resistor
W2
I/O/Z
Emulation pin 0, pullup with a dedicated 20-kΩ resistor
RESET AND INTERRUPTS
K2
I
Device reset
Nonmaskable interrupt
L2
I
Edge-driven (rising edge)
-
U2
External interrupts
External interrupts
T4
Edge-driven
Edge-driven
-
-
I
I
V1
Polarity independently selected via the external interrupt polarity register bits
Polarity independently selected via the external interrupt polarity register bits
-
-
V2
(EXTPOL.[3:0])
Y1
O
Interrupt acknowledge for all active interrupts serviced by the CPU
V4
Active interrupt identification number
A ti
i t
Y2
O
O
Valid during IACK for all active interrupts (not just external)
-
AA1
Encoding order follows the interrupt service fetch packet ordering
Encoding order follows the interrupt-service fetch-packet ordering
-
-
W4
LITTLE ENDIAN/BIG ENDIAN
If high, LENDIAN selects little-endian byte/half-word addressing order within a word
G2
I
If low, LENDIAN selects big-endian addressing
POWER-DOWN STATUS
E2
O
Power-down mode 2 or 3 (active if high)
•
POST OFFICE BOX 1443
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
DESCRIPTION
DESCRIPTION
connection for the low-pass filter
CC
t id
tifi
ti
b
HOUSTON, TEXAS 77251--1443
TMS320C6201
¶
¶
9
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